| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ |
| #define ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_DEC0_CMD |
| * (Prototype: VSI_CMD) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_DEC0_CMD_SWREG0 0x41E0000 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG1 0x41E0004 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG2 0x41E0008 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG3 0x41E000C |
| |
| #define mmDCORE0_DEC0_CMD_SWREG4 0x41E0010 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG5 0x41E0014 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG6 0x41E0018 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG7 0x41E001C |
| |
| #define mmDCORE0_DEC0_CMD_SWREG8 0x41E0020 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG9 0x41E0024 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG10 0x41E0028 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG11 0x41E002C |
| |
| #define mmDCORE0_DEC0_CMD_SWREG12 0x41E0030 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG13 0x41E0034 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG14 0x41E0038 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG15 0x41E003C |
| |
| #define mmDCORE0_DEC0_CMD_SWREG16 0x41E0040 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG17 0x41E0044 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG18 0x41E0048 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG19 0x41E004C |
| |
| #define mmDCORE0_DEC0_CMD_SWREG20 0x41E0050 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG21 0x41E0054 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG22 0x41E0058 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG23 0x41E005C |
| |
| #define mmDCORE0_DEC0_CMD_SWREG24 0x41E0060 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG25 0x41E0064 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG26 0x41E0068 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG64 0x41E0100 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG65 0x41E0104 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG66 0x41E0108 |
| |
| #define mmDCORE0_DEC0_CMD_SWREG67 0x41E010C |
| |
| #endif /* ASIC_REG_DCORE0_DEC0_CMD_REGS_H_ */ |