| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ |
| #define ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DCORE0_MME_QM_ARC_AUX |
| * (Prototype: QMAN_ARC_AUX) |
| ***************************************** |
| */ |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ 0x40C8100 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK 0x40C8104 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_RST_VEC_ADDR 0x40C8108 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DBG_MODE 0x40C810C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM 0x40C8110 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_NUM 0x40C8114 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT 0x40C8118 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x40C811C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CTI_AP_STS 0x40C8120 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x40C8124 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_RST 0x40C8128 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ 0x40C812C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SRAM_LSB_ADDR 0x40C8130 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SRAM_MSB_ADDR 0x40C8134 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_PCIE_LSB_ADDR 0x40C8138 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_PCIE_MSB_ADDR 0x40C813C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_LSB_ADDR 0x40C8140 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_MSB_ADDR 0x40C8144 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM0_LSB_ADDR 0x40C8150 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM0_MSB_ADDR 0x40C8154 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM1_LSB_ADDR 0x40C8158 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM1_MSB_ADDR 0x40C815C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM2_LSB_ADDR 0x40C8160 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM2_MSB_ADDR 0x40C8164 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM3_LSB_ADDR 0x40C8168 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM3_MSB_ADDR 0x40C816C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM0_OFFSET 0x40C8170 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM1_OFFSET 0x40C8174 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM2_OFFSET 0x40C8178 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_HBM3_OFFSET 0x40C817C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x40C8180 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x40C8184 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x40C8188 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x40C818C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x40C8190 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x40C8194 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x40C8198 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x40C819C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40C81A0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40C81A4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40C81A8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40C81AC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40C81B0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40C81B4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40C81B8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40C81BC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_0 0x40C81C0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_1 0x40C81C4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_2 0x40C81C8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_3 0x40C81CC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_4 0x40C81D0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_5 0x40C81D4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_6 0x40C81D8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CONTEXT_ID_7 0x40C81DC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_0 0x40C81E0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_1 0x40C81E4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_2 0x40C81E8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_3 0x40C81EC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_4 0x40C81F0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_5 0x40C81F4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_6 0x40C81F8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7 0x40C81FC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_0 0x40C8200 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_1 0x40C8204 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_2 0x40C8208 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_3 0x40C820C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_4 0x40C8210 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_5 0x40C8214 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_6 0x40C8218 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_7 0x40C821C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_8 0x40C8220 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_9 0x40C8224 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_10 0x40C8228 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_11 0x40C822C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_12 0x40C8230 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_13 0x40C8234 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_14 0x40C8238 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SW_INTR_15 0x40C823C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_0 0x40C8280 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_IRQ_INTR_MASK_1 0x40C8284 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_STS 0x40C8290 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x40C8294 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x40C8298 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x40C829C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40C82A0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40C82A4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40C82A8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_STS 0x40C82B0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40C82B4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40C82B8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40C82BC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40C82C0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40C82C4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40C82C8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40C82CC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40C82D0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40C82E0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40C82E4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40C82E8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40C82EC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40C82F0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40C82F4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0 0x40C8300 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_1 0x40C8304 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_2 0x40C8308 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_3 0x40C830C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_4 0x40C8310 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_5 0x40C8314 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_6 0x40C8318 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_7 0x40C831C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x40C8320 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x40C8324 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x40C8328 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x40C832C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x40C8330 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x40C8334 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x40C8338 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x40C833C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR 0x40C8350 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x40C8354 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR 0x40C8358 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x40C835C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x40C8360 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x40C8364 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x40C8368 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x40C836C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_AXCACHE_OVR 0x40C8370 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_LOCK_OVR 0x40C8374 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_PROT_OVR 0x40C8378 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x40C837C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x40C8380 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x40C8384 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x40C838C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_SEI_INTR_ID 0x40C8390 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR 0x40C8400 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x40C8404 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR 0x40C8408 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x40C840C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_AXCACHE_OVR 0x40C8420 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_LOCK_OVR 0x40C8424 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_PROT_OVR 0x40C8428 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x40C842C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x40C8430 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x40C8434 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x40C843C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBU_SEI_INTR_ID 0x40C8440 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x40C8500 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x40C8504 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x40C8508 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x40C850C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x40C8510 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x40C8514 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x40C8518 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x40C851C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x40C8520 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x40C8524 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x40C8528 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x40C852C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x40C8530 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x40C8534 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x40C8538 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x40C853C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x40C8540 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x40C8544 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x40C8548 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x40C854C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x40C8550 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x40C8554 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x40C8558 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x40C855C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x40C8560 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x40C8564 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x40C8568 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x40C856C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x40C8570 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x40C8574 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x40C8578 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x40C857C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x40C8580 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x40C8584 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x40C8588 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x40C858C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x40C8590 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x40C8594 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x40C8598 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x40C859C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40C85A0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40C85A4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40C85A8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40C85AC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40C85B0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40C85B4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40C85B8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40C85BC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40C85C0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40C85C4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40C85C8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40C85CC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40C85D0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40C85D4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40C85D8 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40C85DC |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40C85E0 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40C85E4 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x40C8620 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x40C8624 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x40C8628 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x40C8630 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x40C8634 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x40C8638 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x40C863C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x40C8640 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x40C8644 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x40C8648 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x40C864C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x40C8650 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x40C8654 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x40C8658 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x40C865C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_AUX2APB_PROT 0x40C8700 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBW_FORK_WIN_EN 0x40C8704 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x40C8708 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x40C870C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x40C8710 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x40C8714 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x40C8718 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x40C871C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x40C8720 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x40C8724 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x40C8728 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x40C872C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x40C8730 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x40C8734 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x40C8738 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x40C873C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_WIN_EN 0x40C8740 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x40C8750 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x40C8754 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x40C8758 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x40C875C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x40C8760 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x40C8764 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x40C8768 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x40C876C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x40C8770 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x40C8774 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x40C8778 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x40C877C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x40C8780 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x40C8784 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x40C8788 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x40C878C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x40C8790 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x40C8794 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x40C8798 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x40C879C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_0 0x40C8800 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_1 0x40C8804 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_2 0x40C8808 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_3 0x40C880C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_4 0x40C8810 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_5 0x40C8814 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_6 0x40C8818 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_7 0x40C881C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_8 0x40C8820 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_9 0x40C8824 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_10 0x40C8828 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_11 0x40C882C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_12 0x40C8830 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_13 0x40C8834 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_14 0x40C8838 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_REGION_CFG_15 0x40C883C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x40C8840 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x40C8844 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x40C8848 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x40C884C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x40C8850 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x40C8854 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x40C8900 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x40C8904 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x40C8908 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x40C890C |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x40C8910 |
| |
| #define mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x40C8920 |
| |
| #endif /* ASIC_REG_DCORE0_MME_QM_ARC_AUX_REGS_H_ */ |