| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_PCIE_DBI_REGS_H_ |
| #define ASIC_REG_PCIE_DBI_REGS_H_ |
| |
| /* |
| ***************************************** |
| * PCIE_DBI |
| * (Prototype: PCIE_DBI) |
| ***************************************** |
| */ |
| |
| #define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0x4C02000 |
| |
| #define mmPCIE_DBI_STATUS_COMMAND_REG 0x4C02004 |
| |
| #define mmPCIE_DBI_CLASS_CODE_REVISION_ID 0x4C02008 |
| |
| #define mmPCIE_DBI_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG 0x4C0200C |
| |
| #define mmPCIE_DBI_BAR0_REG 0x4C02010 |
| |
| #define mmPCIE_DBI_BAR1_REG 0x4C02014 |
| |
| #define mmPCIE_DBI_BAR2_REG 0x4C02018 |
| |
| #define mmPCIE_DBI_BAR3_REG 0x4C0201C |
| |
| #define mmPCIE_DBI_BAR4_REG 0x4C02020 |
| |
| #define mmPCIE_DBI_BAR5_REG 0x4C02024 |
| |
| #define mmPCIE_DBI_CARDBUS_CIS_PTR_REG 0x4C02028 |
| |
| #define mmPCIE_DBI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG 0x4C0202C |
| |
| #define mmPCIE_DBI_EXP_ROM_BASE_ADDR_REG 0x4C02030 |
| |
| #define mmPCIE_DBI_PCI_CAP_PTR_REG 0x4C02034 |
| |
| #define mmPCIE_DBI_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG 0x4C0203C |
| |
| #define mmPCIE_DBI_CAP_ID_NXT_PTR_REG 0x4C02040 |
| |
| #define mmPCIE_DBI_CON_STATUS_REG 0x4C02044 |
| |
| #define mmPCIE_DBI_PCI_MSI_CAP_ID_NEXT_CTRL_REG 0x4C02050 |
| |
| #define mmPCIE_DBI_MSI_CAP_OFF_04H_REG 0x4C02054 |
| |
| #define mmPCIE_DBI_MSI_CAP_OFF_08H_REG 0x4C02058 |
| |
| #define mmPCIE_DBI_MSI_CAP_OFF_0CH_REG 0x4C0205C |
| |
| #define mmPCIE_DBI_MSI_CAP_OFF_10H_REG 0x4C02060 |
| |
| #define mmPCIE_DBI_MSI_CAP_OFF_14H_REG 0x4C02064 |
| |
| #define mmPCIE_DBI_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG 0x4C02070 |
| |
| #define mmPCIE_DBI_DEVICE_CAPABILITIES_REG 0x4C02074 |
| |
| #define mmPCIE_DBI_DEVICE_CONTROL_DEVICE_STATUS 0x4C02078 |
| |
| #define mmPCIE_DBI_LINK_CAPABILITIES_REG 0x4C0207C |
| |
| #define mmPCIE_DBI_LINK_CONTROL_LINK_STATUS_REG 0x4C02080 |
| |
| #define mmPCIE_DBI_DEVICE_CAPABILITIES2_REG 0x4C02094 |
| |
| #define mmPCIE_DBI_DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x4C02098 |
| |
| #define mmPCIE_DBI_LINK_CAPABILITIES2_REG 0x4C0209C |
| |
| #define mmPCIE_DBI_LINK_CONTROL2_LINK_STATUS2_REG 0x4C020A0 |
| |
| #define mmPCIE_DBI_PCI_MSIX_CAP_ID_NEXT_CTRL_REG 0x4C020B0 |
| |
| #define mmPCIE_DBI_MSIX_TABLE_OFFSET_REG 0x4C020B4 |
| |
| #define mmPCIE_DBI_MSIX_PBA_OFFSET_REG 0x4C020B8 |
| |
| #define mmPCIE_DBI_AER_EXT_CAP_HDR_OFF 0x4C02100 |
| |
| #define mmPCIE_DBI_UNCORR_ERR_STATUS_OFF 0x4C02104 |
| |
| #define mmPCIE_DBI_UNCORR_ERR_MASK_OFF 0x4C02108 |
| |
| #define mmPCIE_DBI_UNCORR_ERR_SEV_OFF 0x4C0210C |
| |
| #define mmPCIE_DBI_CORR_ERR_STATUS_OFF 0x4C02110 |
| |
| #define mmPCIE_DBI_CORR_ERR_MASK_OFF 0x4C02114 |
| |
| #define mmPCIE_DBI_ADV_ERR_CAP_CTRL_OFF 0x4C02118 |
| |
| #define mmPCIE_DBI_HDR_LOG_0_OFF 0x4C0211C |
| |
| #define mmPCIE_DBI_HDR_LOG_1_OFF 0x4C02120 |
| |
| #define mmPCIE_DBI_HDR_LOG_2_OFF 0x4C02124 |
| |
| #define mmPCIE_DBI_HDR_LOG_3_OFF 0x4C02128 |
| |
| #define mmPCIE_DBI_TLP_PREFIX_LOG_1_OFF 0x4C02138 |
| |
| #define mmPCIE_DBI_TLP_PREFIX_LOG_2_OFF 0x4C0213C |
| |
| #define mmPCIE_DBI_TLP_PREFIX_LOG_3_OFF 0x4C02140 |
| |
| #define mmPCIE_DBI_TLP_PREFIX_LOG_4_OFF 0x4C02144 |
| |
| #define mmPCIE_DBI_SPCIE_CAP_HEADER_REG 0x4C02148 |
| |
| #define mmPCIE_DBI_LINK_CONTROL3_REG 0x4C0214C |
| |
| #define mmPCIE_DBI_LANE_ERR_STATUS_REG 0x4C02150 |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_0CH_REG 0x4C02154 |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_10H_REG 0x4C02158 |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_14H_REG 0x4C0215C |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_18H_REG 0x4C02160 |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_1CH_REG 0x4C02164 |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_20H_REG 0x4C02168 |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_24H_REG 0x4C0216C |
| |
| #define mmPCIE_DBI_SPCIE_CAP_OFF_28H_REG 0x4C02170 |
| |
| #define mmPCIE_DBI_PL16G_EXT_CAP_HDR_REG 0x4C02178 |
| |
| #define mmPCIE_DBI_PL16G_CAPABILITY_REG 0x4C0217C |
| |
| #define mmPCIE_DBI_PL16G_CONTROL_REG 0x4C02180 |
| |
| #define mmPCIE_DBI_PL16G_STATUS_REG 0x4C02184 |
| |
| #define mmPCIE_DBI_PL16G_LC_DPAR_STATUS_REG 0x4C02188 |
| |
| #define mmPCIE_DBI_PL16G_FIRST_RETIMER_DPAR_STATUS_REG 0x4C0218C |
| |
| #define mmPCIE_DBI_PL16G_SECOND_RETIMER_DPAR_STATUS_REG 0x4C02190 |
| |
| #define mmPCIE_DBI_PL16G_CAP_OFF_20H_REG 0x4C02198 |
| |
| #define mmPCIE_DBI_PL16G_CAP_OFF_24H_REG 0x4C0219C |
| |
| #define mmPCIE_DBI_PL16G_CAP_OFF_28H_REG 0x4C021A0 |
| |
| #define mmPCIE_DBI_PL16G_CAP_OFF_2CH_REG 0x4C021A4 |
| |
| #define mmPCIE_DBI_MARGIN_EXT_CAP_HDR_REG 0x4C021A8 |
| |
| #define mmPCIE_DBI_MARGIN_PORT_CAPABILITIES_STATUS_REG 0x4C021AC |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS0_REG 0x4C021B0 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS1_REG 0x4C021B4 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS2_REG 0x4C021B8 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS3_REG 0x4C021BC |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS4_REG 0x4C021C0 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS5_REG 0x4C021C4 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS6_REG 0x4C021C8 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS7_REG 0x4C021CC |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS8_REG 0x4C021D0 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS9_REG 0x4C021D4 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS10_REG 0x4C021D8 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS11_REG 0x4C021DC |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS12_REG 0x4C021E0 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS13_REG 0x4C021E4 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS14_REG 0x4C021E8 |
| |
| #define mmPCIE_DBI_MARGIN_LANE_CNTRL_STATUS15_REG 0x4C021EC |
| |
| #define mmPCIE_DBI_LTR_CAP_HDR_REG 0x4C021F0 |
| |
| #define mmPCIE_DBI_LTR_LATENCY_REG 0x4C021F4 |
| |
| #define mmPCIE_DBI_RAS_DES_CAP_HEADER_REG 0x4C021F8 |
| |
| #define mmPCIE_DBI_VENDOR_SPECIFIC_HEADER_REG 0x4C021FC |
| |
| #define mmPCIE_DBI_EVENT_COUNTER_CONTROL_REG 0x4C02200 |
| |
| #define mmPCIE_DBI_EVENT_COUNTER_DATA_REG 0x4C02204 |
| |
| #define mmPCIE_DBI_TIME_BASED_ANALYSIS_CONTROL_REG 0x4C02208 |
| |
| #define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_REG 0x4C0220C |
| |
| #define mmPCIE_DBI_TIME_BASED_ANALYSIS_DATA_63_32_REG 0x4C02210 |
| |
| #define mmPCIE_DBI_EINJ_ENABLE_REG 0x4C02228 |
| |
| #define mmPCIE_DBI_EINJ0_CRC_REG 0x4C0222C |
| |
| #define mmPCIE_DBI_EINJ1_SEQNUM_REG 0x4C02230 |
| |
| #define mmPCIE_DBI_EINJ2_DLLP_REG 0x4C02234 |
| |
| #define mmPCIE_DBI_EINJ3_SYMBOL_REG 0x4C02238 |
| |
| #define mmPCIE_DBI_EINJ4_FC_REG 0x4C0223C |
| |
| #define mmPCIE_DBI_EINJ5_SP_TLP_REG 0x4C02240 |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_POINT_H0_REG 0x4C02244 |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_POINT_H1_REG 0x4C02248 |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_POINT_H2_REG 0x4C0224C |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_POINT_H3_REG 0x4C02250 |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H0_REG 0x4C02254 |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H1_REG 0x4C02258 |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H2_REG 0x4C0225C |
| |
| #define mmPCIE_DBI_EINJ6_COMPARE_VALUE_H3_REG 0x4C02260 |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_POINT_H0_REG 0x4C02264 |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_POINT_H1_REG 0x4C02268 |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_POINT_H2_REG 0x4C0226C |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_POINT_H3_REG 0x4C02270 |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H0_REG 0x4C02274 |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H1_REG 0x4C02278 |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H2_REG 0x4C0227C |
| |
| #define mmPCIE_DBI_EINJ6_CHANGE_VALUE_H3_REG 0x4C02280 |
| |
| #define mmPCIE_DBI_EINJ6_TLP_REG 0x4C02284 |
| |
| #define mmPCIE_DBI_SD_CONTROL1_REG 0x4C02298 |
| |
| #define mmPCIE_DBI_SD_CONTROL2_REG 0x4C0229C |
| |
| #define mmPCIE_DBI_SD_STATUS_L1LANE_REG 0x4C022A8 |
| |
| #define mmPCIE_DBI_SD_STATUS_L1LTSSM_REG 0x4C022AC |
| |
| #define mmPCIE_DBI_SD_STATUS_PM_REG 0x4C022B0 |
| |
| #define mmPCIE_DBI_SD_STATUS_L2_REG 0x4C022B4 |
| |
| #define mmPCIE_DBI_SD_STATUS_L3FC_REG 0x4C022B8 |
| |
| #define mmPCIE_DBI_SD_STATUS_L3_REG 0x4C022BC |
| |
| #define mmPCIE_DBI_SD_EQ_CONTROL1_REG 0x4C022C8 |
| |
| #define mmPCIE_DBI_SD_EQ_CONTROL2_REG 0x4C022CC |
| |
| #define mmPCIE_DBI_SD_EQ_CONTROL3_REG 0x4C022D0 |
| |
| #define mmPCIE_DBI_SD_EQ_STATUS1_REG 0x4C022D8 |
| |
| #define mmPCIE_DBI_SD_EQ_STATUS2_REG 0x4C022DC |
| |
| #define mmPCIE_DBI_SD_EQ_STATUS3_REG 0x4C022E0 |
| |
| #define mmPCIE_DBI_DATA_LINK_FEATURE_EXT_HDR_OFF 0x4C022F8 |
| |
| #define mmPCIE_DBI_DATA_LINK_FEATURE_CAP_OFF 0x4C022FC |
| |
| #define mmPCIE_DBI_DATA_LINK_FEATURE_STATUS_OFF 0x4C02300 |
| |
| #define mmPCIE_DBI_ACK_LATENCY_TIMER_OFF 0x4C02700 |
| |
| #define mmPCIE_DBI_VENDOR_SPEC_DLLP_OFF 0x4C02704 |
| |
| #define mmPCIE_DBI_PORT_FORCE_OFF 0x4C02708 |
| |
| #define mmPCIE_DBI_ACK_F_ASPM_CTRL_OFF 0x4C0270C |
| |
| #define mmPCIE_DBI_PORT_LINK_CTRL_OFF 0x4C02710 |
| |
| #define mmPCIE_DBI_LANE_SKEW_OFF 0x4C02714 |
| |
| #define mmPCIE_DBI_TIMER_CTRL_MAX_FUNC_NUM_OFF 0x4C02718 |
| |
| #define mmPCIE_DBI_SYMBOL_TIMER_FILTER_1_OFF 0x4C0271C |
| |
| #define mmPCIE_DBI_FILTER_MASK_2_OFF 0x4C02720 |
| |
| #define mmPCIE_DBI_AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF 0x4C02724 |
| |
| #define mmPCIE_DBI_PL_DEBUG0_OFF 0x4C02728 |
| |
| #define mmPCIE_DBI_PL_DEBUG1_OFF 0x4C0272C |
| |
| #define mmPCIE_DBI_TX_P_FC_CREDIT_STATUS_OFF 0x4C02730 |
| |
| #define mmPCIE_DBI_TX_NP_FC_CREDIT_STATUS_OFF 0x4C02734 |
| |
| #define mmPCIE_DBI_TX_CPL_FC_CREDIT_STATUS_OFF 0x4C02738 |
| |
| #define mmPCIE_DBI_QUEUE_STATUS_OFF 0x4C0273C |
| |
| #define mmPCIE_DBI_VC_TX_ARBI_1_OFF 0x4C02740 |
| |
| #define mmPCIE_DBI_VC_TX_ARBI_2_OFF 0x4C02744 |
| |
| #define mmPCIE_DBI_VC0_P_RX_Q_CTRL_OFF 0x4C02748 |
| |
| #define mmPCIE_DBI_VC0_NP_RX_Q_CTRL_OFF 0x4C0274C |
| |
| #define mmPCIE_DBI_VC0_CPL_RX_Q_CTRL_OFF 0x4C02750 |
| |
| #define mmPCIE_DBI_GEN2_CTRL_OFF 0x4C0280C |
| |
| #define mmPCIE_DBI_PHY_STATUS_OFF 0x4C02810 |
| |
| #define mmPCIE_DBI_PHY_CONTROL_OFF 0x4C02814 |
| |
| #define mmPCIE_DBI_TRGT_MAP_CTRL_OFF 0x4C0281C |
| |
| #define mmPCIE_DBI_CLOCK_GATING_CTRL_OFF 0x4C0288C |
| |
| #define mmPCIE_DBI_GEN3_RELATED_OFF 0x4C02890 |
| |
| #define mmPCIE_DBI_GEN3_EQ_CONTROL_OFF 0x4C028A8 |
| |
| #define mmPCIE_DBI_GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x4C028AC |
| |
| #define mmPCIE_DBI_ORDER_RULE_CTRL_OFF 0x4C028B4 |
| |
| #define mmPCIE_DBI_PIPE_LOOPBACK_CONTROL_OFF 0x4C028B8 |
| |
| #define mmPCIE_DBI_MISC_CONTROL_1_OFF 0x4C028BC |
| |
| #define mmPCIE_DBI_MULTI_LANE_CONTROL_OFF 0x4C028C0 |
| |
| #define mmPCIE_DBI_PHY_INTEROP_CTRL_OFF 0x4C028C4 |
| |
| #define mmPCIE_DBI_TRGT_CPL_LUT_DELETE_ENTRY_OFF 0x4C028C8 |
| |
| #define mmPCIE_DBI_LINK_FLUSH_CONTROL_OFF 0x4C028CC |
| |
| #define mmPCIE_DBI_AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x4C028D0 |
| |
| #define mmPCIE_DBI_AMBA_LINK_TIMEOUT_OFF 0x4C028D4 |
| |
| #define mmPCIE_DBI_AMBA_ORDERING_CTRL_OFF 0x4C028D8 |
| |
| #define mmPCIE_DBI_COHERENCY_CONTROL_1_OFF 0x4C028E0 |
| |
| #define mmPCIE_DBI_COHERENCY_CONTROL_2_OFF 0x4C028E4 |
| |
| #define mmPCIE_DBI_COHERENCY_CONTROL_3_OFF 0x4C028E8 |
| |
| #define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_LOW_OFF 0x4C028F0 |
| |
| #define mmPCIE_DBI_AXI_MSTR_MSG_ADDR_HIGH_OFF 0x4C028F4 |
| |
| #define mmPCIE_DBI_PCIE_VERSION_NUMBER_OFF 0x4C028F8 |
| |
| #define mmPCIE_DBI_PCIE_VERSION_TYPE_OFF 0x4C028FC |
| |
| #define mmPCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF 0x4C02940 |
| |
| #define mmPCIE_DBI_MSIX_ADDRESS_MATCH_HIGH_OFF 0x4C02944 |
| |
| #define mmPCIE_DBI_MSIX_DOORBELL_OFF 0x4C02948 |
| |
| #define mmPCIE_DBI_MSIX_RAM_CTRL_OFF 0x4C0294C |
| |
| #define mmPCIE_DBI_PL_LTR_LATENCY_OFF 0x4C02B30 |
| |
| #define mmPCIE_DBI_AUX_CLK_FREQ_OFF 0x4C02B40 |
| |
| #define mmPCIE_DBI_POWERDOWN_CTRL_STATUS_OFF 0x4C02B48 |
| |
| #define mmPCIE_DBI_PHY_VIEWPORT_CTLSTS_OFF 0x4C02B70 |
| |
| #define mmPCIE_DBI_PHY_VIEWPORT_DATA_OFF 0x4C02B74 |
| |
| #define mmPCIE_DBI_GEN4_LANE_MARGINING_1_OFF 0x4C02B80 |
| |
| #define mmPCIE_DBI_GEN4_LANE_MARGINING_2_OFF 0x4C02B84 |
| |
| #define mmPCIE_DBI_PIPE_RELATED_OFF 0x4C02B90 |
| |
| #define mmPCIE_DBI_RX_SERIALIZATION_Q_CTRL_OFF 0x4C02C00 |
| |
| #endif /* ASIC_REG_PCIE_DBI_REGS_H_ */ |