| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2020 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_PSOC_ETR_REGS_H_ |
| #define ASIC_REG_PSOC_ETR_REGS_H_ |
| |
| /* |
| ***************************************** |
| * PSOC_ETR |
| * (Prototype: ETR) |
| ***************************************** |
| */ |
| |
| #define mmPSOC_ETR_RSZ 0x6C44004 |
| |
| #define mmPSOC_ETR_STS 0x6C4400C |
| |
| #define mmPSOC_ETR_RRD 0x6C44010 |
| |
| #define mmPSOC_ETR_RRP 0x6C44014 |
| |
| #define mmPSOC_ETR_RWP 0x6C44018 |
| |
| #define mmPSOC_ETR_TRG 0x6C4401C |
| |
| #define mmPSOC_ETR_CTL 0x6C44020 |
| |
| #define mmPSOC_ETR_RWD 0x6C44024 |
| |
| #define mmPSOC_ETR_MODE 0x6C44028 |
| |
| #define mmPSOC_ETR_LBUFLEVEL 0x6C4402C |
| |
| #define mmPSOC_ETR_CBUFLEVEL 0x6C44030 |
| |
| #define mmPSOC_ETR_BUFWM 0x6C44034 |
| |
| #define mmPSOC_ETR_RRPHI 0x6C44038 |
| |
| #define mmPSOC_ETR_RWPHI 0x6C4403C |
| |
| #define mmPSOC_ETR_AXICTL 0x6C44110 |
| |
| #define mmPSOC_ETR_DBALO 0x6C44118 |
| |
| #define mmPSOC_ETR_DBAHI 0x6C4411C |
| |
| #define mmPSOC_ETR_FFSR 0x6C44300 |
| |
| #define mmPSOC_ETR_FFCR 0x6C44304 |
| |
| #define mmPSOC_ETR_PSCR 0x6C44308 |
| |
| #define mmPSOC_ETR_ITMISCOP0 0x6C44EE0 |
| |
| #define mmPSOC_ETR_ITTRFLIN 0x6C44EE8 |
| |
| #define mmPSOC_ETR_ITATBDATA0 0x6C44EEC |
| |
| #define mmPSOC_ETR_ITATBCTR2 0x6C44EF0 |
| |
| #define mmPSOC_ETR_ITATBCTR1 0x6C44EF4 |
| |
| #define mmPSOC_ETR_ITATBCTR0 0x6C44EF8 |
| |
| #define mmPSOC_ETR_ITCTRL 0x6C44F00 |
| |
| #define mmPSOC_ETR_CLAIMSET 0x6C44FA0 |
| |
| #define mmPSOC_ETR_CLAIMCLR 0x6C44FA4 |
| |
| #define mmPSOC_ETR_LAR 0x6C44FB0 |
| |
| #define mmPSOC_ETR_LSR 0x6C44FB4 |
| |
| #define mmPSOC_ETR_AUTHSTATUS 0x6C44FB8 |
| |
| #define mmPSOC_ETR_DEVID 0x6C44FC8 |
| |
| #define mmPSOC_ETR_DEVTYPE 0x6C44FCC |
| |
| #define mmPSOC_ETR_PERIPHID4 0x6C44FD0 |
| |
| #define mmPSOC_ETR_PERIPHID5 0x6C44FD4 |
| |
| #define mmPSOC_ETR_PERIPHID6 0x6C44FD8 |
| |
| #define mmPSOC_ETR_PERIPHID7 0x6C44FDC |
| |
| #define mmPSOC_ETR_PERIPHID0 0x6C44FE0 |
| |
| #define mmPSOC_ETR_PERIPHID1 0x6C44FE4 |
| |
| #define mmPSOC_ETR_PERIPHID2 0x6C44FE8 |
| |
| #define mmPSOC_ETR_PERIPHID3 0x6C44FEC |
| |
| #define mmPSOC_ETR_COMPID0 0x6C44FF0 |
| |
| #define mmPSOC_ETR_COMPID1 0x6C44FF4 |
| |
| #define mmPSOC_ETR_COMPID2 0x6C44FF8 |
| |
| #define mmPSOC_ETR_COMPID3 0x6C44FFC |
| |
| #endif /* ASIC_REG_PSOC_ETR_REGS_H_ */ |