| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* Copyright (c) 2020 Microchip Technology Inc */ |
| |
| /dts-v1/; |
| |
| #include "microchip-mpfs.dtsi" |
| |
| /* Clock frequency (in Hz) of the rtcclk */ |
| #define RTCCLK_FREQ 1000000 |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| model = "Microchip PolarFire-SoC Icicle Kit"; |
| compatible = "microchip,mpfs-icicle-kit"; |
| |
| chosen { |
| stdout-path = &serial0; |
| }; |
| |
| cpus { |
| timebase-frequency = <RTCCLK_FREQ>; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x0 0x80000000 0x0 0x40000000>; |
| clocks = <&clkcfg 26>; |
| }; |
| |
| soc { |
| }; |
| }; |
| |
| &serial0 { |
| status = "okay"; |
| }; |
| |
| &serial1 { |
| status = "okay"; |
| }; |
| |
| &serial2 { |
| status = "okay"; |
| }; |
| |
| &serial3 { |
| status = "okay"; |
| }; |
| |
| &sdcard { |
| status = "okay"; |
| }; |
| |
| &emac0 { |
| phy-mode = "sgmii"; |
| phy-handle = <&phy0>; |
| phy0: ethernet-phy@8 { |
| reg = <8>; |
| ti,fifo-depth = <0x01>; |
| }; |
| }; |
| |
| &emac1 { |
| status = "okay"; |
| phy-mode = "sgmii"; |
| phy-handle = <&phy1>; |
| phy1: ethernet-phy@9 { |
| reg = <9>; |
| ti,fifo-depth = <0x01>; |
| }; |
| }; |