| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_ |
| #define ASIC_REG_CPU_CA53_CFG_REGS_H_ |
| |
| /* |
| ***************************************** |
| * CPU_CA53_CFG (Prototype: CA53_CFG) |
| ***************************************** |
| */ |
| |
| #define mmCPU_CA53_CFG_ARM_CFG 0x441100 |
| |
| #define mmCPU_CA53_CFG_RST_ADDR_LSB_0 0x441104 |
| |
| #define mmCPU_CA53_CFG_RST_ADDR_LSB_1 0x441108 |
| |
| #define mmCPU_CA53_CFG_RST_ADDR_MSB_0 0x441114 |
| |
| #define mmCPU_CA53_CFG_RST_ADDR_MSB_1 0x441118 |
| |
| #define mmCPU_CA53_CFG_ARM_RST_CONTROL 0x441124 |
| |
| #define mmCPU_CA53_CFG_ARM_AFFINITY 0x441128 |
| |
| #define mmCPU_CA53_CFG_ARM_DISABLE 0x44112C |
| |
| #define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE 0x441130 |
| |
| #define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG 0x441134 |
| |
| #define mmCPU_CA53_CFG_ARM_PWR_MNG 0x441138 |
| |
| #define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR 0x44113C |
| |
| #define mmCPU_CA53_CFG_ARM_DBG_MODES 0x441140 |
| |
| #define mmCPU_CA53_CFG_ARM_PWR_STAT_0 0x441200 |
| |
| #define mmCPU_CA53_CFG_ARM_PWR_STAT_1 0x441204 |
| |
| #define mmCPU_CA53_CFG_ARM_DBG_STATUS 0x441208 |
| |
| #define mmCPU_CA53_CFG_ARM_MEM_ATTR 0x44120C |
| |
| #define mmCPU_CA53_CFG_ARM_PMU_0 0x441210 |
| |
| #define mmCPU_CA53_CFG_ARM_PMU_1 0x441214 |
| |
| #endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */ |