| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ |
| #define ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ |
| |
| /* |
| ***************************************** |
| * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) |
| ***************************************** |
| */ |
| |
| #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_0 0xC4B000 |
| |
| #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_1 0xC4B004 |
| |
| #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_2 0xC4B008 |
| |
| #define mmPSOC_GLOBAL_CONF_NON_RST_FLOPS_3 0xC4B00C |
| |
| #define mmPSOC_GLOBAL_CONF_PCI_FW_FSM 0xC4B020 |
| |
| #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_RE_START 0xC4B024 |
| |
| #define mmPSOC_GLOBAL_CONF_BTM_FSM 0xC4B028 |
| |
| #define mmPSOC_GLOBAL_CONF_SW_BTM_FSM 0xC4B030 |
| |
| #define mmPSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM 0xC4B034 |
| |
| #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT 0xC4B038 |
| |
| #define mmPSOC_GLOBAL_CONF_SPI_MEM_EN 0xC4B040 |
| |
| #define mmPSOC_GLOBAL_CONF_PRSTN 0xC4B044 |
| |
| #define mmPSOC_GLOBAL_CONF_PCIE_EN 0xC4B048 |
| |
| #define mmPSOC_GLOBAL_CONF_SPI_IMG_STS 0xC4B050 |
| |
| #define mmPSOC_GLOBAL_CONF_BOOT_SEQ_FSM 0xC4B054 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_0 0xC4B100 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_1 0xC4B104 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_2 0xC4B108 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_3 0xC4B10C |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_4 0xC4B110 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_5 0xC4B114 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_6 0xC4B118 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_7 0xC4B11C |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_8 0xC4B120 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_9 0xC4B124 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_10 0xC4B128 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_11 0xC4B12C |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_12 0xC4B130 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_13 0xC4B134 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_14 0xC4B138 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_15 0xC4B13C |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_16 0xC4B140 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_17 0xC4B144 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_18 0xC4B148 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_19 0xC4B14C |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_20 0xC4B150 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_21 0xC4B154 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_22 0xC4B158 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_23 0xC4B15C |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_24 0xC4B160 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_25 0xC4B164 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_26 0xC4B168 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_27 0xC4B16C |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_28 0xC4B170 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_29 0xC4B174 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_30 0xC4B178 |
| |
| #define mmPSOC_GLOBAL_CONF_SCRATCHPAD_31 0xC4B17C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_0 0xC4B200 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_1 0xC4B204 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_2 0xC4B208 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_3 0xC4B20C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_4 0xC4B210 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_5 0xC4B214 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_6 0xC4B218 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_7 0xC4B21C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_8 0xC4B220 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_9 0xC4B224 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_10 0xC4B228 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_11 0xC4B22C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_12 0xC4B230 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_13 0xC4B234 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_14 0xC4B238 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_15 0xC4B23C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_16 0xC4B240 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_17 0xC4B244 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_18 0xC4B248 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_19 0xC4B24C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_20 0xC4B250 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_21 0xC4B254 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_22 0xC4B258 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_23 0xC4B25C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_24 0xC4B260 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_25 0xC4B264 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_26 0xC4B268 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_27 0xC4B26C |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_28 0xC4B270 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_29 0xC4B274 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_30 0xC4B278 |
| |
| #define mmPSOC_GLOBAL_CONF_SEMAPHORE_31 0xC4B27C |
| |
| #define mmPSOC_GLOBAL_CONF_WARM_REBOOT 0xC4B300 |
| |
| #define mmPSOC_GLOBAL_CONF_UBOOT_MAGIC 0xC4B304 |
| |
| #define mmPSOC_GLOBAL_CONF_SPL_SOURCE 0xC4B308 |
| |
| #define mmPSOC_GLOBAL_CONF_I2C_MSTR1_DBG 0xC4B30C |
| |
| #define mmPSOC_GLOBAL_CONF_I2C_SLV 0xC4B310 |
| |
| #define mmPSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK 0xC4B314 |
| |
| #define mmPSOC_GLOBAL_CONF_APP_STATUS 0xC4B320 |
| |
| #define mmPSOC_GLOBAL_CONF_BTL_STS 0xC4B340 |
| |
| #define mmPSOC_GLOBAL_CONF_TIMEOUT_INTR 0xC4B350 |
| |
| #define mmPSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR 0xC4B354 |
| |
| #define mmPSOC_GLOBAL_CONF_PERIPH_INTR 0xC4B358 |
| |
| #define mmPSOC_GLOBAL_CONF_COMB_PERIPH_INTR 0xC4B35C |
| |
| #define mmPSOC_GLOBAL_CONF_AXI_ERR_INTR 0xC4B360 |
| |
| #define mmPSOC_GLOBAL_CONF_TARGETID 0xC4B400 |
| |
| #define mmPSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE 0xC4B420 |
| |
| #define mmPSOC_GLOBAL_CONF_MII_ADDR 0xC4B424 |
| |
| #define mmPSOC_GLOBAL_CONF_MII_SPEED 0xC4B428 |
| |
| #define mmPSOC_GLOBAL_CONF_BOOT_STRAP_PINS 0xC4B430 |
| |
| #define mmPSOC_GLOBAL_CONF_MEM_REPAIR_CTRL 0xC4B450 |
| |
| #define mmPSOC_GLOBAL_CONF_MEM_REPAIR_STS 0xC4B454 |
| |
| #define mmPSOC_GLOBAL_CONF_OUTSTANT_TRANS 0xC4B458 |
| |
| #define mmPSOC_GLOBAL_CONF_MASK_REQ 0xC4B45C |
| |
| #define mmPSOC_GLOBAL_CONF_PRSTN_RST_CFG 0xC4B470 |
| |
| #define mmPSOC_GLOBAL_CONF_SW_ALL_RST_CFG 0xC4B474 |
| |
| #define mmPSOC_GLOBAL_CONF_WD_RST_CFG 0xC4B478 |
| |
| #define mmPSOC_GLOBAL_CONF_MNL_RST_CFG 0xC4B47C |
| |
| #define mmPSOC_GLOBAL_CONF_UNIT_RST_N 0xC4B480 |
| |
| #define mmPSOC_GLOBAL_CONF_PRSTN_MASK 0xC4B484 |
| |
| #define mmPSOC_GLOBAL_CONF_WD_MASK 0xC4B488 |
| |
| #define mmPSOC_GLOBAL_CONF_RST_SRC 0xC4B490 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_0 0xC4B500 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_1 0xC4B504 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_2 0xC4B508 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_3 0xC4B50C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_4 0xC4B510 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_5 0xC4B514 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_6 0xC4B518 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_7 0xC4B51C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_8 0xC4B520 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_9 0xC4B524 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_10 0xC4B528 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_11 0xC4B52C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_12 0xC4B530 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_13 0xC4B534 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_14 0xC4B538 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_15 0xC4B53C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_16 0xC4B540 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_17 0xC4B544 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_18 0xC4B548 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_19 0xC4B54C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_20 0xC4B550 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_21 0xC4B554 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_22 0xC4B558 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_23 0xC4B55C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_24 0xC4B560 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_25 0xC4B564 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_26 0xC4B568 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_27 0xC4B56C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_28 0xC4B570 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_29 0xC4B574 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_30 0xC4B578 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_31 0xC4B57C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_32 0xC4B580 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_33 0xC4B584 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_34 0xC4B588 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_35 0xC4B58C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_36 0xC4B590 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_37 0xC4B594 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_38 0xC4B598 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_39 0xC4B59C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_40 0xC4B5A0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_41 0xC4B5A4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_42 0xC4B5A8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_43 0xC4B5AC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_44 0xC4B5B0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_45 0xC4B5B4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_46 0xC4B5B8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_47 0xC4B5BC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_48 0xC4B5C0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_49 0xC4B5C4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_50 0xC4B5C8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_51 0xC4B5CC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_52 0xC4B5D0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_53 0xC4B5D4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_54 0xC4B5D8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_55 0xC4B5DC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_56 0xC4B5E0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_57 0xC4B5E4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_58 0xC4B5E8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_59 0xC4B5EC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_60 0xC4B5F0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_61 0xC4B5F4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_62 0xC4B5F8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_63 0xC4B5FC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_64 0xC4B600 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_65 0xC4B604 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_66 0xC4B608 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_67 0xC4B60C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_CFG_68 0xC4B610 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_0 0xC4B640 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_1 0xC4B644 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_2 0xC4B648 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_3 0xC4B64C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_4 0xC4B650 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_5 0xC4B654 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_6 0xC4B658 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_7 0xC4B65C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_8 0xC4B660 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_9 0xC4B664 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_10 0xC4B668 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_3V3_CFG_11 0xC4B66C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_0 0xC4B680 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_1 0xC4B684 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_2 0xC4B688 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_3 0xC4B68C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_4 0xC4B690 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_1V8_INPUT_5 0xC4B694 |
| |
| #define mmPSOC_GLOBAL_CONF_BNK3V3_MS 0xC4B6E0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_0 0xC4B700 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_1 0xC4B704 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_2 0xC4B708 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_3 0xC4B70C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_4 0xC4B710 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_5 0xC4B714 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_6 0xC4B718 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_7 0xC4B71C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_8 0xC4B720 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_9 0xC4B724 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_10 0xC4B728 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_11 0xC4B72C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_12 0xC4B730 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_13 0xC4B734 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_14 0xC4B738 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_15 0xC4B73C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_16 0xC4B740 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_17 0xC4B744 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_18 0xC4B748 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_19 0xC4B74C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_20 0xC4B750 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_21 0xC4B754 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_22 0xC4B758 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_23 0xC4B75C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_24 0xC4B760 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_25 0xC4B764 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_26 0xC4B768 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_27 0xC4B76C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_28 0xC4B770 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_29 0xC4B774 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_30 0xC4B778 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_31 0xC4B77C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_32 0xC4B780 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_33 0xC4B784 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_34 0xC4B788 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_35 0xC4B78C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_36 0xC4B790 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_37 0xC4B794 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_38 0xC4B798 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_39 0xC4B79C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_40 0xC4B7A0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_41 0xC4B7A4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_42 0xC4B7A8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_43 0xC4B7AC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_44 0xC4B7B0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_45 0xC4B7B4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_46 0xC4B7B8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_47 0xC4B7BC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_48 0xC4B7C0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_49 0xC4B7C4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_50 0xC4B7C8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_51 0xC4B7CC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_52 0xC4B7D0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_53 0xC4B7D4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_54 0xC4B7D8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_55 0xC4B7DC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_56 0xC4B7E0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_57 0xC4B7E4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_58 0xC4B7E8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_59 0xC4B7EC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_60 0xC4B7F0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_61 0xC4B7F4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_62 0xC4B7F8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_63 0xC4B7FC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_64 0xC4B800 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_65 0xC4B804 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_66 0xC4B808 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_67 0xC4B80C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_68 0xC4B810 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_69 0xC4B814 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_70 0xC4B818 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_71 0xC4B81C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_72 0xC4B820 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_73 0xC4B824 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_74 0xC4B828 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_75 0xC4B82C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_76 0xC4B830 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_77 0xC4B834 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_78 0xC4B838 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_79 0xC4B83C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_80 0xC4B840 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_DEFAULT_81 0xC4B844 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_0 0xC4B900 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_1 0xC4B904 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_2 0xC4B908 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_3 0xC4B90C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_4 0xC4B910 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_5 0xC4B914 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_6 0xC4B918 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_7 0xC4B91C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_8 0xC4B920 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_9 0xC4B924 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_10 0xC4B928 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_11 0xC4B92C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_12 0xC4B930 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_13 0xC4B934 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_14 0xC4B938 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_15 0xC4B93C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_16 0xC4B940 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_17 0xC4B944 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_18 0xC4B948 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_19 0xC4B94C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_20 0xC4B950 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_21 0xC4B954 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_22 0xC4B958 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_23 0xC4B95C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_24 0xC4B960 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_25 0xC4B964 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_26 0xC4B968 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_27 0xC4B96C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_28 0xC4B970 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_29 0xC4B974 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_30 0xC4B978 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_31 0xC4B97C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_32 0xC4B980 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_33 0xC4B984 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_34 0xC4B988 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_35 0xC4B98C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_36 0xC4B990 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_37 0xC4B994 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_38 0xC4B998 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_39 0xC4B99C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_40 0xC4B9A0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_41 0xC4B9A4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_42 0xC4B9A8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_43 0xC4B9AC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_44 0xC4B9B0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_45 0xC4B9B4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_46 0xC4B9B8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_47 0xC4B9BC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_48 0xC4B9C0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_49 0xC4B9C4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_50 0xC4B9C8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_51 0xC4B9CC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_52 0xC4B9D0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_53 0xC4B9D4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_54 0xC4B9D8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_55 0xC4B9DC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_56 0xC4B9E0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_57 0xC4B9E4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_58 0xC4B9E8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_59 0xC4B9EC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_60 0xC4B9F0 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_61 0xC4B9F4 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_62 0xC4B9F8 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_63 0xC4B9FC |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_64 0xC4BA00 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_65 0xC4BA04 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_66 0xC4BA08 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_67 0xC4BA0C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_68 0xC4BA10 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_69 0xC4BA14 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_70 0xC4BA18 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_71 0xC4BA1C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_72 0xC4BA20 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_73 0xC4BA24 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_74 0xC4BA28 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_75 0xC4BA2C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_76 0xC4BA30 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_77 0xC4BA34 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_78 0xC4BA38 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_79 0xC4BA3C |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_80 0xC4BA40 |
| |
| #define mmPSOC_GLOBAL_CONF_PAD_SEL_81 0xC4BA44 |
| |
| #endif /* ASIC_REG_PSOC_GLOBAL_CONF_REGS_H_ */ |