arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree file for the J722S MAIN domain peripherals
 *
 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <dt-bindings/phy/phy-cadence.h>
#include <dt-bindings/phy/phy-ti.h>

/ {
	serdes_refclk: clk-0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
};

&cbass_main {
	serdes_wiz0: phy@f000000 {
		compatible = "ti,am64-wiz-10g";
		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <1>;
		#reset-cells = <1>;
		#clock-cells = <1>;

		assigned-clocks = <&k3_clks 279 1>;
		assigned-clock-parents = <&k3_clks 279 5>;

		serdes0: serdes@f000000 {
			compatible = "ti,j721e-serdes-10g";
			reg = <0x0f000000 0x00010000>;
			reg-names = "torrent_phy";
			resets = <&serdes_wiz0 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
			clock-names = "refclk", "phy_en_refclk";
			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 279 1>,
						 <&k3_clks 279 1>,
						 <&k3_clks 279 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;

			status = "disabled"; /* Needs lane config */
		};
	};

	serdes_wiz1: phy@f010000 {
		compatible = "ti,am64-wiz-10g";
		ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <1>;
		#reset-cells = <1>;
		#clock-cells = <1>;

		assigned-clocks = <&k3_clks 280 1>;
		assigned-clock-parents = <&k3_clks 280 5>;

		serdes1: serdes@f010000 {
			compatible = "ti,j721e-serdes-10g";
			reg = <0x0f010000 0x00010000>;
			reg-names = "torrent_phy";
			resets = <&serdes_wiz1 0>;
			reset-names = "torrent_reset";
			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
			clock-names = "refclk", "phy_en_refclk";
			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
			assigned-clock-parents = <&k3_clks 280 1>,
						 <&k3_clks 280 1>,
						 <&k3_clks 280 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;

			status = "disabled"; /* Needs lane config */
		};
	};

	pcie0_rc: pcie@f102000 {
		compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
		reg = <0x00 0x0f102000 0x00 0x1000>,
		      <0x00 0x0f100000 0x00 0x400>,
		      <0x00 0x0d000000 0x00 0x00800000>,
		      <0x00 0x68000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		max-link-speed = <3>;
		num-lanes = <1>;
		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
		clock-names = "fck", "pcie_refclk";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb010>;
		cdns,no-bar-match-nbits = <64>;
		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		status = "disabled";
	};

	usbss1: usb@f920000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x0f920000 0x00 0x100>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		usb1: usb@31200000{
			compatible = "cdns,usb3";
			reg = <0x00 0x31200000 0x00 0x10000>,
			      <0x00 0x31210000 0x00 0x10000>,
			      <0x00 0x31220000 0x00 0x10000>;
			reg-names = "otg",
				    "xhci",
				    "dev";
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
			interrupt-names = "host",
					  "peripheral",
					  "otg";
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};
};

&main_conf {
	serdes_ln_ctrl: mux-controller@4080 {
		compatible = "reg-mux";
		reg = <0x4080 0x14>;
		#mux-control-cells = <1>;
		mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
				<0x10 0x3>; /* SERDES1 lane0 select */
	};

	audio_refclk1: clock@82e4 {
		compatible = "ti,am62-audio-refclk";
		reg = <0x82e4 0x4>;
		clocks = <&k3_clks 157 18>;
		assigned-clocks = <&k3_clks 157 18>;
		assigned-clock-parents = <&k3_clks 157 33>;
		#clock-cells = <0>;
	};
};

&wkup_conf {
	pcie0_ctrl: pcie0-ctrl@4070 {
		compatible = "ti,j784s4-pcie-ctrl", "syscon";
		reg = <0x4070 0x4>;
	};
};

&oc_sram {
	reg = <0x00 0x70000000 0x00 0x40000>;
	ranges = <0x00 0x00 0x70000000 0x40000>;
};

&inta_main_dmss {
	ti,interrupt-ranges = <7 71 21>;
};

&main_pmx0 {
	pinctrl-single,gpio-range =
		<&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>,
		<&main_pmx0_range 33 55 PIN_GPIO_RANGE_IOPAD>,
		<&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>,
		<&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>,
		<&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>,
		<&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>;

	main_pmx0_range: gpio-range {
		#pinctrl-single,gpio-range-cells = <3>;
	};
};

&main_gpio0 {
	gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
			<&main_pmx0 70 72 17>;
	ti,ngpio = <87>;
};

&main_gpio1 {
	gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
			<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
	ti,ngpio = <73>;
};