arch/arm64/boot/dts/qcom/sm6350.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
 */

#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	interrupt-parent = <&intc>;
	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
					compatible = "cache";
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x100>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_100>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			L2_100: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x200>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_200>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			L2_200: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x300>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_300>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			L2_300: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x400>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_400>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			L2_400: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x500>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_500>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			#cooling-cells = <2>;
			L2_500: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};

		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x600>;
			enable-method = "psci";
			capacity-dmips-mhz = <1894>;
			dynamic-power-coefficient = <703>;
			next-level-cache = <&L2_600>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			L2_600: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x700>;
			enable-method = "psci";
			capacity-dmips-mhz = <1894>;
			dynamic-power-coefficient = <703>;
			next-level-cache = <&L2_700>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			#cooling-cells = <2>;
			L2_700: l2-cache {
				compatible = "cache";
				next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

				core6 {
					cpu = <&CPU6>;
				};

				core7 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-sm6350", "qcom,scm";
			#reset-cells = <1>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: memory@80000000 {
			reg = <0 0x80000000 0 0x600000>;
			no-map;
		};

		xbl_aop_mem: memory@80700000 {
			reg = <0 0x80700000 0 0x160000>;
			no-map;
		};

		cmd_db: memory@80860000 {
			compatible = "qcom,cmd-db";
			reg = <0 0x80860000 0 0x20000>;
			no-map;
		};

		sec_apps_mem: memory@808ff000 {
			reg = <0 0x808ff000 0 0x1000>;
			no-map;
		};

		smem_mem: memory@80900000 {
			reg = <0 0x80900000 0 0x200000>;
			no-map;
		};

		cdsp_sec_mem: memory@80b00000 {
			reg = <0 0x80b00000 0 0x1e00000>;
			no-map;
		};

		pil_camera_mem: memory@86000000 {
			reg = <0 0x86000000 0 0x500000>;
			no-map;
		};

		pil_npu_mem: memory@86500000 {
			reg = <0 0x86500000 0 0x500000>;
			no-map;
		};

		pil_video_mem: memory@86a00000 {
			reg = <0 0x86a00000 0 0x500000>;
			no-map;
		};

		pil_cdsp_mem: memory@86f00000 {
			reg = <0 0x86f00000 0 0x1e00000>;
			no-map;
		};

		pil_adsp_mem: memory@88d00000 {
			reg = <0 0x88d00000 0 0x2800000>;
			no-map;
		};

		wlan_fw_mem: memory@8b500000 {
			reg = <0 0x8b500000 0 0x200000>;
			no-map;
		};

		pil_ipa_fw_mem: memory@8b700000 {
			reg = <0 0x8b700000 0 0x10000>;
			no-map;
		};

		pil_ipa_gsi_mem: memory@8b710000 {
			reg = <0 0x8b710000 0 0x5400>;
			no-map;
		};

		pil_gpu_mem: memory@8b715400 {
			reg = <0 0x8b715400 0 0x2000>;
			no-map;
		};

		pil_modem_mem: memory@8b800000 {
			reg = <0 0x8b800000 0 0xf800000>;
			no-map;
		};

		cont_splash_memory: memory@a0000000 {
			reg = <0 0xa0000000 0 0x2300000>;
			no-map;
		};

		dfps_data_memory: memory@a2300000 {
			reg = <0 0xa2300000 0 0x100000>;
			no-map;
		};

		removed_region: memory@c0000000 {
			reg = <0 0xc0000000 0 0x3900000>;
			no-map;
		};

		debug_region: memory@ffb00000 {
			reg = <0 0xffb00000 0 0xc0000>;
			no-map;
		};

		last_log_region: memory@ffbc0000 {
			reg = <0 0xffbc0000 0 0x40000>;
			no-map;
		};

		ramoops: ramoops@ffc00000 {
			compatible = "removed-dma-pool", "ramoops";
			reg = <0 0xffc00000 0 0x00100000>;
			record-size = <0x1000>;
			console-size = <0x40000>;
			ftrace-size = <0x0>;
			msg-size = <0x20000 0x20000>;
			cc-size = <0x0>;
			no-map;
		};

		cmdline_region: memory@ffd00000 {
			reg = <0 0xffd00000 0 0x1000>;
			no-map;
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	soc: soc@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x10 0>;
		dma-ranges = <0 0 0 0 0x10 0>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sm6350";
			reg = <0 0x00100000 0 0x1f0000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clock-names = "bi_tcxo",
				      "bi_tcxo_ao",
				      "sleep_clk";
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>;
		};

		ipcc: mailbox@408000 {
			compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
			reg = <0 0x00408000 0 0x1000>;
			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#mbox-cells = <2>;
		};

		rng: rng@793000 {
			compatible = "qcom,prng-ee";
			reg = <0 0x00793000 0 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		sdhc_1: sdhci@7c4000 {
			compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x007c4000 0 0x1000>,
				<0 0x007c5000 0 0x1000>,
				<0 0x007c8000 0 0x8000>;
			reg-names = "hc", "cqhci", "ice";

			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "iface", "core", "xo";
			qcom,dll-config = <0x000f642c>;
			qcom,ddr-config = <0x80040868>;
			power-domains = <&rpmhpd 0>;
			operating-points-v2 = <&sdhc1_opp_table>;
			bus-width = <8>;
			non-removable;
			supports-cqe;

			status = "disabled";

			sdhc1_opp_table: sdhc1-opp-table {
				compatible = "operating-points-v2";

				opp-19200000 {
					opp-hz = /bits/ 64 <19200000>;
					required-opps = <&rpmhpd_opp_min_svs>;
				};

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-384000000 {
					opp-hz = /bits/ 64 <384000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};
			};
		};

		qupv3_id_1: geniqup@9c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x9c0000 0x0 0x2000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			#address-cells = <2>;
			#size-cells = <2>;
			iommus = <&apps_smmu 0x4c3 0x0>;
			ranges;
			status = "disabled";

			uart2: serial@98c000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0 0x98c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart2_default>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x0 0x01f40000 0x0 0x40000>;
			#hwlock-cells = <1>;
		};

		sdhc_2: sdhci@8804000 {
			compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x08804000 0 0x1000>;

			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "iface", "core", "xo";
			qcom,dll-config = <0x0007642c>;
			qcom,ddr-config = <0x80040868>;
			power-domains = <&rpmhpd 0>;
			operating-points-v2 = <&sdhc2_opp_table>;
			bus-width = <4>;

			status = "disabled";

			sdhc2_opp_table: sdhc2-opp-table {
				compatible = "operating-points-v2";

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};

				opp-202000000 {
					opp-hz = /bits/ 64 <202000000>;
					required-opps = <&rpmhpd_opp_nom>;
				};
			};
		};

		usb_1_hsphy: phy@88e3000 {
			compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
			reg = <0 0x088e3000 0 0x400>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		};

		usb_1_qmpphy: phy@88e9000 {
			compatible = "qcom,sc7180-qmp-usb3-dp-phy";
			reg = <0 0x088e9000 0 0x200>,
			      <0 0x088e8000 0 0x40>,
			      <0 0x088ea000 0 0x200>;
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&rpmhcc RPMH_QLINK_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
				 <&xo_board>;
			clock-names = "aux", "ref", "com_aux", "cfg_ahb";

			resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
				 <&gcc GCC_USB3_PHY_PRIM_BCR>;
			reset-names = "phy", "common";

			usb_1_ssphy: usb3-phy@88e9200 {
				reg = <0 0x088e9200 0 0x200>,
				      <0 0x088e9400 0 0x200>,
				      <0 0x088e9c00 0 0x400>,
				      <0 0x088e9600 0 0x200>,
				      <0 0x088e9800 0 0x200>,
				      <0 0x088e9a00 0 0x100>;
				#clock-cells = <0>;
				#phy-cells = <0>;
				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_phy_pipe_clk_src";
			};

			dp_phy: dp-phy@88ea200 {
				reg = <0 0x088ea200 0 0x200>,
				      <0 0x088ea400 0 0x200>,
				      <0 0x088eac00 0 0x400>,
				      <0 0x088ea600 0 0x200>,
				      <0 0x088ea800 0 0x200>,
				      <0 0x088eaa00 0 0x100>;
				#phy-cells = <0>;
				#clock-cells = <1>;
				clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
				clock-names = "pipe0";
				clock-output-names = "usb3_phy_pipe_clk_src";
			};
		};

		system-cache-controller@9200000 {
			compatible = "qcom,sm6350-llcc";
			reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
			reg-names = "llcc_base", "llcc_broadcast_base";
		};

		usb_1: usb@a6f8800 {
			compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
			reg = <0 0x0a6f8800 0 0x400>;
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
			clock-names = "cfg_noc", "core", "iface", "mock_utmi",
				      "sleep";

			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
					  "dm_hs_phy_irq", "ss_phy_irq";

			power-domains = <&gcc USB30_PRIM_GDSC>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;

			usb_1_dwc3: usb@a600000 {
				compatible = "snps,dwc3";
				reg = <0 0x0a600000 0 0xcd00>;
				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x540 0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				snps,has-lpm-erratum;
				snps,hird-threshold = /bits/ 8 <0x10>;
				phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,sm6350-pdc", "qcom,pdc";
			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
			qcom,pdc-ranges = <0 480 94>, <94 609 31>,
					  <125 63 1>, <126 655 12>, <138 139 15>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		tsens0: thermal-sensor@c263000 {
			compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
			reg = <0 0x0c263000 0 0x1ff>, /* TM */
			      <0 0x0c222000 0 0x8>; /* SROT */
			#qcom,sensors = <16>;
			interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
				     <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		tsens1: thermal-sensor@c265000 {
			compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
			reg = <0 0x0c265000 0 0x1ff>, /* TM */
			      <0 0x0c223000 0 0x8>; /* SROT */
			#qcom,sensors = <16>;
			interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
				     <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		aoss_qmp: power-controller@c300000 {
			compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
			reg = <0 0x0c300000 0 0x1000>;
			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
						     IRQ_TYPE_EDGE_RISING>;
			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;

			#clock-cells = <0>;
			#power-domain-cells = <1>;
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0 0xc440000 0 0x1100>,
			      <0 0xc600000 0 0x2000000>,
			      <0 0xe600000 0 0x100000>,
			      <0 0xe700000 0 0xa0000>,
			      <0 0xc40a000 0 0x26000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,sm6350-tlmm";
			reg = <0 0x0f100000 0 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&tlmm 0 0 157>;

			qup_uart2_default: qup-uart2-default {
				pins = "gpio25", "gpio26";
				function = "qup13_f2";
				drive-strength = <2>;
				bias-disable;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
			reg = <0 0x15000000 0 0x100000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
		};

		watchdog@17c10000 {
			compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
			reg = <0 0x17c10000 0 0x1000>;
			clocks = <&sleep_clk>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
		};

		timer@17c20000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x0 0x17c20000 0x0 0x1000>;
			clock-frequency = <19200000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			frame@17c21000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17c21000 0x0 0x1000>,
				      <0x0 0x17c22000 0x0 0x1000>;
			};

			frame@17c23000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17c23000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17c25000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17c25000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17c27000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17c27000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17c29000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17c29000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17c2b000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17c2b000 0x0 0x1000>;
				status = "disabled";
			};

			frame@17c2d000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x17c2d000 0x0 0x1000>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@18200000 {
			compatible = "qcom,rpmh-rsc";
			label = "apps_rsc";
			reg = <0x0 0x18200000 0x0 0x10000>,
				<0x0 0x18210000 0x0 0x10000>,
				<0x0 0x18220000 0x0 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
					  <WAKE_TCS 3>, <CONTROL_TCS 1>;

			rpmhcc: clock-controller {
				compatible = "qcom,sm6350-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,sm6350-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp1 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp2 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp3 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp5 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp8 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp10 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};

			apps_bcm_voter: bcm_voter {
				compatible = "qcom,bcm-voter";
			};
		};

		cpufreq_hw: cpufreq@18323000 {
			compatible = "qcom,cpufreq-hw";
			reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
			reg-names = "freq-domain0", "freq-domain1";
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
			clock-names = "xo", "alternate";

			#freq-domain-cells = <1>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		clock-frequency = <19200000>;
		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};
};