| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * dts file for Xilinx ZynqMP ZCU104 |
| * |
| * (C) Copyright 2017 - 2021, Xilinx, Inc. |
| * |
| * Michal Simek <michal.simek@xilinx.com> |
| */ |
| |
| /dts-v1/; |
| |
| #include "zynqmp.dtsi" |
| #include "zynqmp-clk-ccf.dtsi" |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> |
| #include <dt-bindings/phy/phy.h> |
| |
| / { |
| model = "ZynqMP ZCU104 RevA"; |
| compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp"; |
| |
| aliases { |
| ethernet0 = &gem3; |
| i2c0 = &i2c1; |
| mmc0 = &sdhci1; |
| nvmem0 = &eeprom; |
| rtc0 = &rtc; |
| serial0 = &uart0; |
| serial1 = &uart1; |
| serial2 = &dcc; |
| spi0 = &qspi; |
| usb0 = &usb0; |
| }; |
| |
| chosen { |
| bootargs = "earlycon"; |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory@0 { |
| device_type = "memory"; |
| reg = <0x0 0x0 0x0 0x80000000>; |
| }; |
| |
| clock_8t49n287_5: clk125 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <125000000>; |
| }; |
| |
| clock_8t49n287_2: clk26 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <26000000>; |
| }; |
| |
| clock_8t49n287_3: clk27 { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <27000000>; |
| }; |
| }; |
| |
| &can1 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_can1_default>; |
| }; |
| |
| &dcc { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan1 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan2 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan3 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan4 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan5 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan6 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan7 { |
| status = "okay"; |
| }; |
| |
| &fpd_dma_chan8 { |
| status = "okay"; |
| }; |
| |
| &gem3 { |
| status = "okay"; |
| phy-handle = <&phy0>; |
| phy-mode = "rgmii-id"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gem3_default>; |
| phy0: ethernet-phy@c { |
| reg = <0xc>; |
| ti,rx-internal-delay = <0x8>; |
| ti,tx-internal-delay = <0xa>; |
| ti,fifo-depth = <0x1>; |
| ti,dp83867-rxctrl-strap-quirk; |
| }; |
| }; |
| |
| &gpio { |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| status = "okay"; |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1_default>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; |
| sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; |
| |
| /* Another connection to this bus via PL i2c via PCA9306 - u45 */ |
| i2c-mux@74 { /* u34 */ |
| compatible = "nxp,pca9548"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x74>; |
| i2c@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| /* |
| * IIC_EEPROM 1kB memory which uses 256B blocks |
| * where every block has different address. |
| * 0 - 256B address 0x54 |
| * 256B - 512B address 0x55 |
| * 512B - 768B address 0x56 |
| * 768B - 1024B address 0x57 |
| */ |
| eeprom: eeprom@54 { /* u23 */ |
| compatible = "atmel,24c08"; |
| reg = <0x54>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| }; |
| |
| i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| /* 8T49N287 - u182 */ |
| }; |
| |
| i2c@2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <2>; |
| irps5401_43: irps5401@43 { /* IRPS5401 - u175 */ |
| compatible = "infineon,irps5401"; |
| reg = <0x43>; /* pmbus / i2c 0x13 */ |
| }; |
| irps5401_44: irps5401@44 { /* IRPS5401 - u180 */ |
| compatible = "infineon,irps5401"; |
| reg = <0x44>; /* pmbus / i2c 0x14 */ |
| }; |
| }; |
| |
| i2c@4 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <4>; |
| tca6416_u97: gpio@20 { |
| compatible = "ti,tca6416"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| /* |
| * IRQ not connected |
| * Lines: |
| * 0 - IRPS5401_ALERT_B |
| * 1 - HDMI_8T49N241_INT_ALM |
| * 2 - MAX6643_OT_B |
| * 3 - MAX6643_FANFAIL_B |
| * 5 - IIC_MUX_RESET_B |
| * 6 - GEM3_EXP_RESET_B |
| * 7 - FMC_LPC_PRSNT_M2C_B |
| * 4, 10 - 17 - not connected |
| */ |
| }; |
| }; |
| |
| i2c@5 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <5>; |
| }; |
| |
| i2c@7 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <7>; |
| }; |
| |
| /* 3, 6 not connected */ |
| }; |
| }; |
| |
| &pinctrl0 { |
| status = "okay"; |
| |
| pinctrl_can1_default: can1-default { |
| mux { |
| function = "can1"; |
| groups = "can1_6_grp"; |
| }; |
| |
| conf { |
| groups = "can1_6_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| drive-strength = <12>; |
| }; |
| |
| conf-rx { |
| pins = "MIO25"; |
| bias-high-impedance; |
| }; |
| |
| conf-tx { |
| pins = "MIO24"; |
| bias-disable; |
| }; |
| }; |
| |
| pinctrl_i2c1_default: i2c1-default { |
| mux { |
| groups = "i2c1_4_grp"; |
| function = "i2c1"; |
| }; |
| |
| conf { |
| groups = "i2c1_4_grp"; |
| bias-pull-up; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| drive-strength = <12>; |
| }; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1-gpio { |
| mux { |
| groups = "gpio0_16_grp", "gpio0_17_grp"; |
| function = "gpio0"; |
| }; |
| |
| conf { |
| groups = "gpio0_16_grp", "gpio0_17_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| drive-strength = <12>; |
| }; |
| }; |
| |
| pinctrl_gem3_default: gem3-default { |
| mux { |
| function = "ethernet3"; |
| groups = "ethernet3_0_grp"; |
| }; |
| |
| conf { |
| groups = "ethernet3_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| drive-strength = <12>; |
| }; |
| |
| conf-rx { |
| pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74", |
| "MIO75"; |
| bias-high-impedance; |
| low-power-disable; |
| }; |
| |
| conf-tx { |
| pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68", |
| "MIO69"; |
| bias-disable; |
| low-power-enable; |
| }; |
| |
| mux-mdio { |
| function = "mdio3"; |
| groups = "mdio3_0_grp"; |
| }; |
| |
| conf-mdio { |
| groups = "mdio3_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| bias-disable; |
| }; |
| }; |
| |
| pinctrl_sdhci1_default: sdhci1-default { |
| mux { |
| groups = "sdio1_0_grp"; |
| function = "sdio1"; |
| }; |
| |
| conf { |
| groups = "sdio1_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| bias-disable; |
| drive-strength = <12>; |
| }; |
| |
| mux-cd { |
| groups = "sdio1_cd_0_grp"; |
| function = "sdio1_cd"; |
| }; |
| |
| conf-cd { |
| groups = "sdio1_cd_0_grp"; |
| bias-high-impedance; |
| bias-pull-up; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| }; |
| }; |
| |
| pinctrl_uart0_default: uart0-default { |
| mux { |
| groups = "uart0_4_grp"; |
| function = "uart0"; |
| }; |
| |
| conf { |
| groups = "uart0_4_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| drive-strength = <12>; |
| }; |
| |
| conf-rx { |
| pins = "MIO18"; |
| bias-high-impedance; |
| }; |
| |
| conf-tx { |
| pins = "MIO19"; |
| bias-disable; |
| }; |
| }; |
| |
| pinctrl_uart1_default: uart1-default { |
| mux { |
| groups = "uart1_5_grp"; |
| function = "uart1"; |
| }; |
| |
| conf { |
| groups = "uart1_5_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| drive-strength = <12>; |
| }; |
| |
| conf-rx { |
| pins = "MIO21"; |
| bias-high-impedance; |
| }; |
| |
| conf-tx { |
| pins = "MIO20"; |
| bias-disable; |
| }; |
| }; |
| |
| pinctrl_usb0_default: usb0-default { |
| mux { |
| groups = "usb0_0_grp"; |
| function = "usb0"; |
| }; |
| |
| conf { |
| groups = "usb0_0_grp"; |
| slew-rate = <SLEW_RATE_SLOW>; |
| power-source = <IO_STANDARD_LVCMOS18>; |
| drive-strength = <12>; |
| }; |
| |
| conf-rx { |
| pins = "MIO52", "MIO53", "MIO55"; |
| bias-high-impedance; |
| }; |
| |
| conf-tx { |
| pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", |
| "MIO60", "MIO61", "MIO62", "MIO63"; |
| bias-disable; |
| }; |
| }; |
| }; |
| |
| &psgtr { |
| status = "okay"; |
| /* nc, sata, usb3, dp */ |
| clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>; |
| clock-names = "ref1", "ref2", "ref3"; |
| }; |
| |
| &qspi { |
| status = "okay"; |
| flash@0 { |
| compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x0>; |
| spi-tx-bus-width = <1>; |
| spi-rx-bus-width = <4>; |
| spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
| }; |
| }; |
| |
| &rtc { |
| status = "okay"; |
| }; |
| |
| &sata { |
| status = "okay"; |
| /* SATA OOB timing settings */ |
| ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
| ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
| ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
| ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
| ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; |
| ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; |
| ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; |
| ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; |
| phy-names = "sata-phy"; |
| phys = <&psgtr 3 PHY_TYPE_SATA 1 1>; |
| }; |
| |
| /* SD1 with level shifter */ |
| &sdhci1 { |
| status = "okay"; |
| no-1-8-v; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sdhci1_default>; |
| xlnx,mio-bank = <1>; |
| disable-wp; |
| }; |
| |
| &uart0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart0_default>; |
| }; |
| |
| &uart1 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1_default>; |
| }; |
| |
| /* ULPI SMSC USB3320 */ |
| &usb0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usb0_default>; |
| phy-names = "usb3-phy"; |
| phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; |
| }; |
| |
| &dwc3_0 { |
| status = "okay"; |
| dr_mode = "host"; |
| snps,usb3_lpm_capable; |
| maximum-speed = "super-speed"; |
| }; |
| |
| &watchdog0 { |
| status = "okay"; |
| }; |
| |
| &zynqmp_dpdma { |
| status = "okay"; |
| }; |
| |
| &zynqmp_dpsub { |
| status = "okay"; |
| phy-names = "dp-phy0", "dp-phy1"; |
| phys = <&psgtr 1 PHY_TYPE_DP 0 3>, |
| <&psgtr 0 PHY_TYPE_DP 1 3>; |
| }; |
