# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) | |
%YAML 1.2 | |
--- | |
$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# | |
$schema: http://devicetree.org/meta-schemas/core.yaml# | |
title: MediaTek PCIe PHY | |
maintainers: | |
- Jianjun Wang <jianjun.wang@mediatek.com> | |
description: | | |
The PCIe PHY supports physical layer functionality for PCIe Gen3 port. | |
properties: | |
compatible: | |
const: mediatek,mt8195-pcie-phy | |
reg: | |
maxItems: 1 | |
reg-names: | |
items: | |
- const: sif | |
"#phy-cells": | |
const: 0 | |
nvmem-cells: | |
maxItems: 7 | |
description: | |
Phandles to nvmem cell that contains the efuse data, if unspecified, | |
default value is used. | |
nvmem-cell-names: | |
items: | |
- const: glb_intr | |
- const: tx_ln0_pmos | |
- const: tx_ln0_nmos | |
- const: rx_ln0 | |
- const: tx_ln1_pmos | |
- const: tx_ln1_nmos | |
- const: rx_ln1 | |
power-domains: | |
maxItems: 1 | |
required: | |
- compatible | |
- reg | |
- reg-names | |
- "#phy-cells" | |
additionalProperties: false | |
examples: | |
- | | |
phy@11e80000 { | |
compatible = "mediatek,mt8195-pcie-phy"; | |
#phy-cells = <0>; | |
reg = <0x11e80000 0x10000>; | |
reg-names = "sif"; | |
nvmem-cells = <&pciephy_glb_intr>, | |
<&pciephy_tx_ln0_pmos>, | |
<&pciephy_tx_ln0_nmos>, | |
<&pciephy_rx_ln0>, | |
<&pciephy_tx_ln1_pmos>, | |
<&pciephy_tx_ln1_nmos>, | |
<&pciephy_rx_ln1>; | |
nvmem-cell-names = "glb_intr", "tx_ln0_pmos", | |
"tx_ln0_nmos", "rx_ln0", | |
"tx_ln1_pmos", "tx_ln1_nmos", | |
"rx_ln1"; | |
power-domains = <&spm 2>; | |
}; |