| // SPDX-License-Identifier: GPL-2.0 |
| #include <dt-bindings/clock/ingenic,jz4740-cgu.h> |
| #include <dt-bindings/clock/ingenic,tcu.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "ingenic,jz4740"; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "ingenic,xburst-mxu1.0"; |
| reg = <0>; |
| |
| clocks = <&cgu JZ4740_CLK_CCLK>; |
| clock-names = "cpu"; |
| }; |
| }; |
| |
| cpuintc: interrupt-controller { |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| compatible = "mti,cpu-interrupt-controller"; |
| }; |
| |
| intc: interrupt-controller@10001000 { |
| compatible = "ingenic,jz4740-intc"; |
| reg = <0x10001000 0x14>; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| interrupt-parent = <&cpuintc>; |
| interrupts = <2>; |
| }; |
| |
| ext: ext { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| |
| rtc: rtc { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| |
| cgu: jz4740-cgu@10000000 { |
| compatible = "ingenic,jz4740-cgu"; |
| reg = <0x10000000 0x100>; |
| |
| clocks = <&ext>, <&rtc>; |
| clock-names = "ext", "rtc"; |
| |
| #clock-cells = <1>; |
| }; |
| |
| tcu: timer@10002000 { |
| compatible = "ingenic,jz4740-tcu", "simple-mfd"; |
| reg = <0x10002000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x10002000 0x1000>; |
| |
| #clock-cells = <1>; |
| |
| clocks = <&cgu JZ4740_CLK_RTC>, |
| <&cgu JZ4740_CLK_EXT>, |
| <&cgu JZ4740_CLK_PCLK>, |
| <&cgu JZ4740_CLK_TCU>; |
| clock-names = "rtc", "ext", "pclk", "tcu"; |
| |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <23 22 21>; |
| |
| watchdog: watchdog@0 { |
| compatible = "ingenic,jz4740-watchdog"; |
| reg = <0x0 0xc>; |
| |
| clocks = <&tcu TCU_CLK_WDT>; |
| clock-names = "wdt"; |
| }; |
| |
| pwm: pwm@40 { |
| compatible = "ingenic,jz4740-pwm"; |
| reg = <0x40 0x80>; |
| |
| #pwm-cells = <3>; |
| |
| clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, |
| <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, |
| <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>, |
| <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>; |
| clock-names = "timer0", "timer1", "timer2", "timer3", |
| "timer4", "timer5", "timer6", "timer7"; |
| }; |
| }; |
| |
| rtc_dev: rtc@10003000 { |
| compatible = "ingenic,jz4740-rtc"; |
| reg = <0x10003000 0x40>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <15>; |
| |
| clocks = <&cgu JZ4740_CLK_RTC>; |
| clock-names = "rtc"; |
| }; |
| |
| pinctrl: pin-controller@10010000 { |
| compatible = "ingenic,jz4740-pinctrl"; |
| reg = <0x10010000 0x400>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| gpa: gpio@0 { |
| compatible = "ingenic,jz4740-gpio"; |
| reg = <0>; |
| |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 0 32>; |
| #gpio-cells = <2>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <28>; |
| }; |
| |
| gpb: gpio@1 { |
| compatible = "ingenic,jz4740-gpio"; |
| reg = <1>; |
| |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 32 32>; |
| #gpio-cells = <2>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <27>; |
| }; |
| |
| gpc: gpio@2 { |
| compatible = "ingenic,jz4740-gpio"; |
| reg = <2>; |
| |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 64 32>; |
| #gpio-cells = <2>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <26>; |
| }; |
| |
| gpd: gpio@3 { |
| compatible = "ingenic,jz4740-gpio"; |
| reg = <3>; |
| |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 96 32>; |
| #gpio-cells = <2>; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <25>; |
| }; |
| }; |
| |
| aic: audio-controller@10020000 { |
| compatible = "ingenic,jz4740-i2s"; |
| reg = <0x10020000 0x38>; |
| |
| #sound-dai-cells = <0>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <18>; |
| |
| clocks = <&cgu JZ4740_CLK_AIC>, |
| <&cgu JZ4740_CLK_I2S>, |
| <&cgu JZ4740_CLK_EXT>, |
| <&cgu JZ4740_CLK_PLL_HALF>; |
| clock-names = "aic", "i2s", "ext", "pll half"; |
| |
| dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>; |
| dma-names = "rx", "tx"; |
| }; |
| |
| codec: audio-codec@100200a4 { |
| compatible = "ingenic,jz4740-codec"; |
| reg = <0x10020080 0x8>; |
| |
| #sound-dai-cells = <0>; |
| |
| clocks = <&cgu JZ4740_CLK_AIC>; |
| clock-names = "aic"; |
| }; |
| |
| mmc: mmc@10021000 { |
| compatible = "ingenic,jz4740-mmc"; |
| reg = <0x10021000 0x1000>; |
| |
| clocks = <&cgu JZ4740_CLK_MMC>; |
| clock-names = "mmc"; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <14>; |
| |
| dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>; |
| dma-names = "rx", "tx"; |
| |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| cap-sdio-irq; |
| }; |
| |
| uart0: serial@10030000 { |
| compatible = "ingenic,jz4740-uart"; |
| reg = <0x10030000 0x100>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <9>; |
| |
| clocks = <&ext>, <&cgu JZ4740_CLK_UART0>; |
| clock-names = "baud", "module"; |
| }; |
| |
| uart1: serial@10031000 { |
| compatible = "ingenic,jz4740-uart"; |
| reg = <0x10031000 0x100>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <8>; |
| |
| clocks = <&ext>, <&cgu JZ4740_CLK_UART1>; |
| clock-names = "baud", "module"; |
| }; |
| |
| adc: adc@10070000 { |
| compatible = "ingenic,jz4740-adc"; |
| reg = <0x10070000 0x30>; |
| #io-channel-cells = <1>; |
| |
| clocks = <&cgu JZ4740_CLK_ADC>; |
| clock-names = "adc"; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <12>; |
| }; |
| |
| nemc: memory-controller@13010000 { |
| compatible = "ingenic,jz4740-nemc"; |
| reg = <0x13010000 0x54>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges = <1 0 0x18000000 0x4000000>, |
| <2 0 0x14000000 0x4000000>, |
| <3 0 0x0c000000 0x4000000>, |
| <4 0 0x08000000 0x4000000>; |
| |
| clocks = <&cgu JZ4740_CLK_MCLK>; |
| }; |
| |
| ecc: ecc-controller@13010100 { |
| compatible = "ingenic,jz4740-ecc"; |
| reg = <0x13010100 0x2C>; |
| |
| clocks = <&cgu JZ4740_CLK_MCLK>; |
| }; |
| |
| dmac: dma-controller@13020000 { |
| compatible = "ingenic,jz4740-dma"; |
| reg = <0x13020000 0xbc>, <0x13020300 0x14>; |
| #dma-cells = <2>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <20>; |
| |
| clocks = <&cgu JZ4740_CLK_DMA>; |
| }; |
| |
| uhc: usb@13030000 { |
| compatible = "ingenic,jz4740-ohci", "generic-ohci"; |
| reg = <0x13030000 0x1000>; |
| |
| clocks = <&cgu JZ4740_CLK_UHC>; |
| assigned-clocks = <&cgu JZ4740_CLK_UHC>; |
| assigned-clock-rates = <48000000>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <3>; |
| |
| status = "disabled"; |
| }; |
| |
| udc: usb@13040000 { |
| compatible = "ingenic,jz4740-musb"; |
| reg = <0x13040000 0x10000>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <24>; |
| interrupt-names = "mc"; |
| |
| clocks = <&cgu JZ4740_CLK_UDC>; |
| clock-names = "udc"; |
| }; |
| |
| lcd: lcd-controller@13050000 { |
| compatible = "ingenic,jz4740-lcd"; |
| reg = <0x13050000 0x1000>; |
| |
| interrupt-parent = <&intc>; |
| interrupts = <30>; |
| |
| clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>; |
| clock-names = "lcd_pclk", "lcd"; |
| }; |
| }; |
