Documentation/devicetree/bindings/ata/imx-sata.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/imx-sata.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Freescale i.MX AHCI SATA Controller

maintainers:
  - Shawn Guo <shawn.guo@linaro.org>

description: |
  The Freescale i.MX SATA controller mostly conforms to the AHCI interface
  with some special extensions at integration level.

properties:
  compatible:
    enum:
      - fsl,imx53-ahci
      - fsl,imx6q-ahci
      - fsl,imx6qp-ahci
      - fsl,imx8qm-ahci

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    minItems: 2
    items:
      - description: sata clock
      - description: sata reference clock
      - description: ahb clock

  clock-names:
    minItems: 2
    items:
      - const: sata
      - const: sata_ref
      - const: ahb

  fsl,transmit-level-mV:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: transmit voltage level, in millivolts.

  fsl,transmit-boost-mdB:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: transmit boost level, in milli-decibels.

  fsl,transmit-atten-16ths:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: transmit attenuation, in 16ths.

  fsl,receive-eq-mdB:
    $ref: /schemas/types.yaml#/definitions/uint32
    description: receive equalisation, in milli-decibels.

  fsl,no-spread-spectrum:
    $ref: /schemas/types.yaml#/definitions/flag
    description: if present, disable spread-spectrum clocking on the SATA link.

  phys:
    items:
      - description: phandle to SATA PHY.
          Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
          calibration result will be stored, passed through second lane, and
          shared with all three lanes PHY. The first two lanes PHY are used as
          calibration PHYs, although only the third lane PHY is used by SATA.
      - description: phandle to the first lane PHY of i.MX8QM.
      - description: phandle to the second lane PHY of i.MX8QM.

  phy-names:
    items:
      - const: sata-phy
      - const: cali-phy0
      - const: cali-phy1

  power-domains:
    maxItems: 1

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx53-ahci
              - fsl,imx6q-ahci
              - fsl,imx6qp-ahci
    then:
      properties:
        clock-names:
          minItems: 3

  - if:
      properties:
        compatible:
          contains:
            enum:
              - fsl,imx8qm-ahci
    then:
      properties:
        clock-names:
          minItems: 2

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx6qdl-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    sata@2200000 {
        compatible = "fsl,imx6q-ahci";
        reg = <0x02200000 0x4000>;
        interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&clks IMX6QDL_CLK_SATA>,
                 <&clks IMX6QDL_CLK_SATA_REF_100M>,
                 <&clks IMX6QDL_CLK_AHB>;
        clock-names = "sata", "sata_ref", "ahb";
    };