Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright 2022 NXP
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP S32G2 pin controller

maintainers:
  - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com>
  - Chester Lin <chester62515@gmail.com>

description: |
  S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2),
  whose memory map is split into two regions:
    SIUL2_0 @ 0x4009c000
    SIUL2_1 @ 0x44010000

  Every SIUL2 region has multiple register types, and here only MSCR and
  IMCR registers need to be revealed for kernel to configure pinmux.

  Please note that some register indexes are reserved in S32G2, such as
  MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.

properties:
  compatible:
    enum:
      - nxp,s32g2-siul2-pinctrl

  reg:
    description: |
      A list of MSCR/IMCR register regions to be reserved.
      - MSCR (Multiplexed Signal Configuration Register)
        An MSCR register can configure the associated pin as either a GPIO pin
        or a function output pin depends on the selected signal source.
      - IMCR (Input Multiplexed Signal Configuration Register)
        An IMCR register can configure the associated pin as function input
        pin depends on the selected signal source.
    items:
      - description: MSCR registers group 0 in SIUL2_0
      - description: MSCR registers group 1 in SIUL2_1
      - description: MSCR registers group 2 in SIUL2_1
      - description: IMCR registers group 0 in SIUL2_0
      - description: IMCR registers group 1 in SIUL2_1
      - description: IMCR registers group 2 in SIUL2_1

patternProperties:
  '-pins$':
    type: object
    additionalProperties: false

    patternProperties:
      '-grp[0-9]$':
        type: object
        allOf:
          - $ref: pinmux-node.yaml#
          - $ref: pincfg-node.yaml#
        description: |
          Pinctrl node's client devices specify pin muxes using subnodes,
          which in turn use the standard properties below.

        properties:
          bias-disable: true
          bias-high-impedance: true
          bias-pull-up: true
          bias-pull-down: true
          drive-open-drain: true
          input-enable: true
          output-enable: true

          pinmux:
            description: |
              An integer array for representing pinmux configurations of
              a device. Each integer consists of a PIN_ID and a 4-bit
              selected signal source(SSS) as IOMUX setting, which is
              calculated as: pinmux = (PIN_ID << 4 | SSS)

          slew-rate:
            description: Supported slew rate based on Fmax values (MHz)
            enum: [83, 133, 150, 166, 208]

        additionalProperties: false

required:
  - compatible
  - reg

additionalProperties: false

examples:
  - |
    pinctrl@4009c240 {
        compatible = "nxp,s32g2-siul2-pinctrl";

              /* MSCR0-MSCR101 registers on siul2_0 */
        reg = <0x4009c240 0x198>,
              /* MSCR112-MSCR122 registers on siul2_1 */
              <0x44010400 0x2c>,
              /* MSCR144-MSCR190 registers on siul2_1 */
              <0x44010480 0xbc>,
              /* IMCR0-IMCR83 registers on siul2_0 */
              <0x4009ca40 0x150>,
              /* IMCR119-IMCR397 registers on siul2_1 */
              <0x44010c1c 0x45c>,
              /* IMCR430-IMCR495 registers on siul2_1 */
              <0x440110f8 0x108>;

        llce-can0-pins {
            llce-can0-grp0 {
                pinmux = <0x2b0>;
                input-enable;
                slew-rate = <208>;
            };

            llce-can0-grp1 {
                pinmux = <0x2c2>;
                output-enable;
                slew-rate = <208>;
            };
        };
    };
...