Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml

# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner Memory Bus (MBUS) controller

maintainers:
  - Chen-Yu Tsai <wens@csie.org>
  - Maxime Ripard <mripard@kernel.org>

description: |
  The MBUS controller drives the MBUS that other devices in the SoC
  will use to perform DMA. It also has a register interface that
  allows to monitor and control the bandwidth and priorities for
  masters on that bus.

  Each device having to perform their DMA through the MBUS must have
  the interconnects and interconnect-names properties set to the MBUS
  controller and with "dma-mem" as the interconnect name.

properties:
  "#interconnect-cells":
    const: 1
    description:
      The content of the cell is the MBUS ID.

  compatible:
    enum:
      - allwinner,sun5i-a13-mbus
      - allwinner,sun8i-a33-mbus
      - allwinner,sun8i-a50-mbus
      - allwinner,sun8i-a83t-mbus
      - allwinner,sun8i-h3-mbus
      - allwinner,sun8i-r40-mbus
      - allwinner,sun8i-v3s-mbus
      - allwinner,sun8i-v536-mbus
      - allwinner,sun20i-d1-mbus
      - allwinner,sun50i-a64-mbus
      - allwinner,sun50i-a100-mbus
      - allwinner,sun50i-h5-mbus
      - allwinner,sun50i-h6-mbus
      - allwinner,sun50i-h616-mbus
      - allwinner,sun50i-r329-mbus

  reg:
    minItems: 1
    items:
      - description: MBUS interconnect/bandwidth limit/PMU registers
      - description: DRAM controller/PHY registers

  reg-names:
    minItems: 1
    items:
      - const: mbus
      - const: dram

  clocks:
    minItems: 1
    items:
      - description: MBUS interconnect module clock
      - description: DRAM controller/PHY module clock
      - description: Register bus clock, shared by MBUS and DRAM

  clock-names:
    minItems: 1
    items:
      - const: mbus
      - const: dram
      - const: bus

  interrupts:
    maxItems: 1
    description:
      MBUS PMU activity interrupt.

  dma-ranges:
    description:
      See section 2.3.9 of the DeviceTree Specification.

  '#address-cells': true

  '#size-cells': true

required:
  - "#interconnect-cells"
  - compatible
  - reg
  - clocks
  - dma-ranges

if:
  not:
    properties:
      compatible:
        contains:
          enum:
            - allwinner,sun5i-a13-mbus
            - allwinner,sun8i-r40-mbus

then:
  properties:
    reg:
      minItems: 2

    reg-names:
      minItems: 2

    clocks:
      minItems: 3

    clock-names:
      minItems: 3

  required:
    - reg-names
    - clock-names

else:
  properties:
    reg:
      maxItems: 1

    reg-names:
      maxItems: 1

    clocks:
      maxItems: 1

    clock-names:
      maxItems: 1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/sun50i-a64-ccu.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    dram-controller@1c01000 {
        compatible = "allwinner,sun5i-a13-mbus";
        reg = <0x01c01000 0x1000>;
        clocks = <&ccu CLK_MBUS>;
        #address-cells = <1>;
        #size-cells = <1>;
        dma-ranges = <0x00000000 0x40000000 0x20000000>;
        #interconnect-cells = <1>;
    };

  - |
    dram-controller@1c62000 {
        compatible = "allwinner,sun50i-a64-mbus";
        reg = <0x01c62000 0x1000>,
              <0x01c63000 0x1000>;
        reg-names = "mbus", "dram";
        clocks = <&ccu CLK_MBUS>,
                 <&ccu CLK_DRAM>,
                 <&ccu CLK_BUS_DRAM>;
        clock-names = "mbus", "dram", "bus";
        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
        #address-cells = <1>;
        #size-cells = <1>;
        dma-ranges = <0x00000000 0x40000000 0xc0000000>;
        #interconnect-cells = <1>;
    };

...