| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Clock bindings for Freescale i.MX7ULP System Clock Generation (SCG) modules |
| |
| maintainers: |
| - A.s. Dong <aisheng.dong@nxp.com> |
| |
| description: | |
| i.MX7ULP Clock functions are under joint control of the System |
| Clock Generation (SCG) modules, Peripheral Clock Control (PCC) |
| modules, and Core Mode Controller (CMC)1 blocks |
| |
| The clocking scheme provides clear separation between M4 domain |
| and A7 domain. Except for a few clock sources shared between two |
| domains, such as the System Oscillator clock, the Slow IRC (SIRC), |
| and and the Fast IRC clock (FIRCLK), clock sources and clock |
| management are separated and contained within each domain. |
| |
| M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. |
| A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. |
| |
| Note: this binding doc is only for A7 clock domain. |
| |
| The System Clock Generation (SCG) is responsible for clock generation |
| and distribution across this device. Functions performed by the SCG |
| include: clock reference selection, generation of clock used to derive |
| processor, system, peripheral bus and external memory interface clocks, |
| source selection for peripheral clocks and control of power saving |
| clock gating mode. |
| |
| The clock consumer should specify the desired clock by having the clock |
| ID in its "clocks" phandle cell. |
| See include/dt-bindings/clock/imx7ulp-clock.h for the full list of |
| i.MX7ULP clock IDs of each module. |
| |
| properties: |
| compatible: |
| const: fsl,imx7ulp-scg1 |
| |
| reg: |
| maxItems: 1 |
| |
| '#clock-cells': |
| const: 1 |
| |
| clocks: |
| items: |
| - description: rtc osc |
| - description: system osc |
| - description: slow internal reference clock |
| - description: fast internal reference clock |
| - description: usb PLL |
| |
| clock-names: |
| items: |
| - const: rosc |
| - const: sosc |
| - const: sirc |
| - const: firc |
| - const: upll |
| |
| required: |
| - compatible |
| - reg |
| - '#clock-cells' |
| - clocks |
| - clock-names |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/clock/imx7ulp-clock.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| clock-controller@403e0000 { |
| compatible = "fsl,imx7ulp-scg1"; |
| reg = <0x403e0000 0x10000>; |
| clocks = <&rosc>, <&sosc>, <&sirc>, |
| <&firc>, <&upll>; |
| clock-names = "rosc", "sosc", "sirc", |
| "firc", "upll"; |
| #clock-cells = <1>; |
| }; |