| # SPDX-License-Identifier: GPL-2.0-only |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: ARM SMMUv3 Architecture Implementation |
| |
| maintainers: |
| - Will Deacon <will@kernel.org> |
| - Robin Murphy <Robin.Murphy@arm.com> |
| |
| description: |+ |
| The SMMUv3 architecture is a significant departure from previous |
| revisions, replacing the MMIO register interface with in-memory command |
| and event queues and adding support for the ATS and PRI components of |
| the PCIe specification. |
| |
| properties: |
| $nodename: |
| pattern: "^iommu@[0-9a-f]*" |
| compatible: |
| const: arm,smmu-v3 |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| minItems: 1 |
| maxItems: 4 |
| |
| interrupt-names: |
| oneOf: |
| - const: combined |
| description: |
| The combined interrupt is optional, and should only be provided if the |
| hardware supports just a single, combined interrupt line. |
| If provided, then the combined interrupt will be used in preference to |
| any others. |
| - minItems: 1 |
| items: |
| - enum: |
| - eventq # Event Queue not empty |
| - gerror # Global Error activated |
| - const: gerror |
| - enum: |
| - cmdq-sync # CMD_SYNC complete |
| - priq # PRI Queue not empty |
| - enum: |
| - cmdq-sync |
| - priq |
| |
| '#iommu-cells': |
| const: 1 |
| |
| dma-coherent: |
| description: | |
| Present if page table walks made by the SMMU are cache coherent with the |
| CPU. |
| |
| NOTE: this only applies to the SMMU itself, not masters connected |
| upstream of the SMMU. |
| |
| msi-parent: true |
| |
| hisilicon,broken-prefetch-cmd: |
| type: boolean |
| description: Avoid sending CMD_PREFETCH_* commands to the SMMU. |
| |
| cavium,cn9900-broken-page1-regspace: |
| type: boolean |
| description: |
| Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS |
| register access with page 0 offsets. Set for Cavium ThunderX2 silicon that |
| doesn't support SMMU page1 register space. |
| |
| required: |
| - compatible |
| - reg |
| - '#iommu-cells' |
| |
| additionalProperties: false |
| |
| examples: |
| - |+ |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| iommu@2b400000 { |
| compatible = "arm,smmu-v3"; |
| reg = <0x2b400000 0x20000>; |
| interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; |
| dma-coherent; |
| #iommu-cells = <1>; |
| msi-parent = <&its 0xff0000>; |
| }; |