| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/sound/mediatek,mt8188-afe.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: MediaTek AFE PCM controller for mt8188 |
| |
| maintainers: |
| - Trevor Wu <trevor.wu@mediatek.com> |
| |
| properties: |
| compatible: |
| const: mediatek,mt8188-afe |
| |
| reg: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| resets: |
| maxItems: 1 |
| |
| reset-names: |
| const: audiosys |
| |
| memory-region: |
| maxItems: 1 |
| description: | |
| Shared memory region for AFE memif. A "shared-dma-pool". |
| See ../reserved-memory/reserved-memory.yaml for details. |
| |
| mediatek,topckgen: |
| $ref: /schemas/types.yaml#/definitions/phandle |
| description: The phandle of the mediatek topckgen controller |
| |
| mediatek,infracfg: |
| $ref: /schemas/types.yaml#/definitions/phandle |
| description: The phandle of the mediatek infracfg controller |
| |
| power-domains: |
| maxItems: 1 |
| |
| clocks: |
| items: |
| - description: 26M clock |
| - description: audio pll1 clock |
| - description: audio pll2 clock |
| - description: clock divider for i2si1_mck |
| - description: clock divider for i2si2_mck |
| - description: clock divider for i2so1_mck |
| - description: clock divider for i2so2_mck |
| - description: clock divider for dptx_mck |
| - description: a1sys hoping clock |
| - description: audio intbus clock |
| - description: audio hires clock |
| - description: audio local bus clock |
| - description: mux for dptx_mck |
| - description: mux for i2so1_mck |
| - description: mux for i2so2_mck |
| - description: mux for i2si1_mck |
| - description: mux for i2si2_mck |
| - description: audio 26m clock |
| - description: audio pll1 divide 4 |
| - description: audio pll2 divide 4 |
| - description: clock divider for iec |
| - description: mux for a2sys clock |
| - description: mux for aud_iec |
| |
| clock-names: |
| items: |
| - const: clk26m |
| - const: apll1 |
| - const: apll2 |
| - const: apll12_div0 |
| - const: apll12_div1 |
| - const: apll12_div2 |
| - const: apll12_div3 |
| - const: apll12_div9 |
| - const: top_a1sys_hp |
| - const: top_aud_intbus |
| - const: top_audio_h |
| - const: top_audio_local_bus |
| - const: top_dptx |
| - const: top_i2so1 |
| - const: top_i2so2 |
| - const: top_i2si1 |
| - const: top_i2si2 |
| - const: adsp_audio_26m |
| - const: apll1_d4 |
| - const: apll2_d4 |
| - const: apll12_div4 |
| - const: top_a2sys |
| - const: top_aud_iec |
| |
| mediatek,etdm-in1-cowork-source: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| etdm modules can share the same external clock pin. Specify |
| which etdm clock source is required by this etdm in module. |
| enum: |
| - 1 # etdm2_in |
| - 2 # etdm1_out |
| - 3 # etdm2_out |
| |
| mediatek,etdm-in2-cowork-source: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| etdm modules can share the same external clock pin. Specify |
| which etdm clock source is required by this etdm in module. |
| enum: |
| - 0 # etdm1_in |
| - 2 # etdm1_out |
| - 3 # etdm2_out |
| |
| mediatek,etdm-out1-cowork-source: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| etdm modules can share the same external clock pin. Specify |
| which etdm clock source is required by this etdm out module. |
| enum: |
| - 0 # etdm1_in |
| - 1 # etdm2_in |
| - 3 # etdm2_out |
| |
| mediatek,etdm-out2-cowork-source: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| etdm modules can share the same external clock pin. Specify |
| which etdm clock source is required by this etdm out module. |
| enum: |
| - 0 # etdm1_in |
| - 1 # etdm2_in |
| - 2 # etdm1_out |
| |
| patternProperties: |
| "^mediatek,etdm-in[1-2]-chn-disabled$": |
| $ref: /schemas/types.yaml#/definitions/uint8-array |
| minItems: 1 |
| maxItems: 16 |
| description: |
| This is a list of channel IDs which should be disabled. |
| By default, all data received from ETDM pins will be outputted to |
| memory. etdm in supports disable_out in direct mode(w/o interconn), |
| so user can disable the specified channels by the property. |
| uniqueItems: true |
| items: |
| minimum: 0 |
| maximum: 15 |
| |
| "^mediatek,etdm-in[1-2]-multi-pin-mode$": |
| type: boolean |
| description: if present, the etdm data mode is I2S. |
| |
| "^mediatek,etdm-out[1-3]-multi-pin-mode$": |
| type: boolean |
| description: if present, the etdm data mode is I2S. |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - resets |
| - reset-names |
| - mediatek,topckgen |
| - mediatek,infracfg |
| - power-domains |
| - clocks |
| - clock-names |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| afe@10b10000 { |
| compatible = "mediatek,mt8188-afe"; |
| reg = <0x10b10000 0x10000>; |
| interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; |
| resets = <&watchdog 14>; |
| reset-names = "audiosys"; |
| memory-region = <&snd_dma_mem_reserved>; |
| mediatek,topckgen = <&topckgen>; |
| mediatek,infracfg = <&infracfg_ao>; |
| power-domains = <&spm 13>; //MT8188_POWER_DOMAIN_AUDIO |
| mediatek,etdm-in2-cowork-source = <2>; |
| mediatek,etdm-out2-cowork-source = <0>; |
| mediatek,etdm-in1-multi-pin-mode; |
| mediatek,etdm-in1-chn-disabled = /bits/ 8 <0x0 0x2>; |
| clocks = <&clk26m>, |
| <&apmixedsys 9>, //CLK_APMIXED_APLL1 |
| <&apmixedsys 10>, //CLK_APMIXED_APLL2 |
| <&topckgen 186>, //CLK_TOP_APLL12_CK_DIV0 |
| <&topckgen 187>, //CLK_TOP_APLL12_CK_DIV1 |
| <&topckgen 188>, //CLK_TOP_APLL12_CK_DIV2 |
| <&topckgen 189>, //CLK_TOP_APLL12_CK_DIV3 |
| <&topckgen 191>, //CLK_TOP_APLL12_CK_DIV9 |
| <&topckgen 83>, //CLK_TOP_A1SYS_HP |
| <&topckgen 31>, //CLK_TOP_AUD_INTBUS |
| <&topckgen 32>, //CLK_TOP_AUDIO_H |
| <&topckgen 69>, //CLK_TOP_AUDIO_LOCAL_BUS |
| <&topckgen 81>, //CLK_TOP_DPTX |
| <&topckgen 77>, //CLK_TOP_I2SO1 |
| <&topckgen 78>, //CLK_TOP_I2SO2 |
| <&topckgen 79>, //CLK_TOP_I2SI1 |
| <&topckgen 80>, //CLK_TOP_I2SI2 |
| <&adsp_audio26m 0>, //CLK_AUDIODSP_AUDIO26M |
| <&topckgen 132>, //CLK_TOP_APLL1_D4 |
| <&topckgen 133>, //CLK_TOP_APLL2_D4 |
| <&topckgen 183>, //CLK_TOP_APLL12_CK_DIV4 |
| <&topckgen 84>, //CLK_TOP_A2SYS |
| <&topckgen 82>; //CLK_TOP_AUD_IEC>; |
| clock-names = "clk26m", |
| "apll1", |
| "apll2", |
| "apll12_div0", |
| "apll12_div1", |
| "apll12_div2", |
| "apll12_div3", |
| "apll12_div9", |
| "top_a1sys_hp", |
| "top_aud_intbus", |
| "top_audio_h", |
| "top_audio_local_bus", |
| "top_dptx", |
| "top_i2so1", |
| "top_i2so2", |
| "top_i2si1", |
| "top_i2si2", |
| "adsp_audio_26m", |
| "apll1_d4", |
| "apll2_d4", |
| "apll12_div4", |
| "top_a2sys", |
| "top_aud_iec"; |
| }; |
| |
| ... |
