| /* |
| * Samsung's Exynos4210 SoC device tree source |
| * |
| * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
| * http://www.samsung.com |
| * Copyright (c) 2010-2011 Linaro Ltd. |
| * www.linaro.org |
| * |
| * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210 |
| * based board files can include this file and provide values for board specfic |
| * bindings. |
| * |
| * Note: This file does not include device nodes for all the controllers in |
| * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional |
| * nodes can be added to this file. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #include "exynos4.dtsi" |
| #include "exynos4210-pinctrl.dtsi" |
| #include "exynos4-cpu-thermal.dtsi" |
| |
| / { |
| compatible = "samsung,exynos4210", "samsung,exynos4"; |
| |
| aliases { |
| pinctrl0 = &pinctrl_0; |
| pinctrl1 = &pinctrl_1; |
| pinctrl2 = &pinctrl_2; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@900 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0x900>; |
| clocks = <&clock CLK_ARM_CLK>; |
| clock-names = "cpu"; |
| clock-latency = <160000>; |
| |
| operating-points = < |
| 1200000 1250000 |
| 1000000 1150000 |
| 800000 1075000 |
| 500000 975000 |
| 400000 975000 |
| 200000 950000 |
| >; |
| cooling-min-level = <4>; |
| cooling-max-level = <2>; |
| #cooling-cells = <2>; /* min followed by max */ |
| }; |
| |
| cpu@901 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a9"; |
| reg = <0x901>; |
| }; |
| }; |
| |
| sysram: sysram@02020000 { |
| compatible = "mmio-sram"; |
| reg = <0x02020000 0x20000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x02020000 0x20000>; |
| |
| smp-sysram@0 { |
| compatible = "samsung,exynos4210-sysram"; |
| reg = <0x0 0x1000>; |
| }; |
| |
| smp-sysram@1f000 { |
| compatible = "samsung,exynos4210-sysram-ns"; |
| reg = <0x1f000 0x1000>; |
| }; |
| }; |
| |
| pd_lcd1: lcd1-power-domain@10023CA0 { |
| compatible = "samsung,exynos4210-pd"; |
| reg = <0x10023CA0 0x20>; |
| #power-domain-cells = <0>; |
| }; |
| |
| l2c: l2-cache-controller@10502000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x10502000 0x1000>; |
| cache-unified; |
| cache-level = <2>; |
| arm,tag-latency = <2 2 1>; |
| arm,data-latency = <2 2 1>; |
| }; |
| |
| mct: mct@10050000 { |
| compatible = "samsung,exynos4210-mct"; |
| reg = <0x10050000 0x800>; |
| interrupt-parent = <&mct_map>; |
| interrupts = <0>, <1>, <2>, <3>, <4>, <5>; |
| clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; |
| clock-names = "fin_pll", "mct"; |
| |
| mct_map: mct-map { |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| interrupt-map = <0 &gic 0 57 0>, |
| <1 &gic 0 69 0>, |
| <2 &combiner 12 6>, |
| <3 &combiner 12 7>, |
| <4 &gic 0 42 0>, |
| <5 &gic 0 48 0>; |
| }; |
| }; |
| |
| clock: clock-controller@10030000 { |
| compatible = "samsung,exynos4210-clock"; |
| reg = <0x10030000 0x20000>; |
| #clock-cells = <1>; |
| }; |
| |
| pinctrl_0: pinctrl@11400000 { |
| compatible = "samsung,exynos4210-pinctrl"; |
| reg = <0x11400000 0x1000>; |
| interrupts = <0 47 0>; |
| }; |
| |
| pinctrl_1: pinctrl@11000000 { |
| compatible = "samsung,exynos4210-pinctrl"; |
| reg = <0x11000000 0x1000>; |
| interrupts = <0 46 0>; |
| |
| wakup_eint: wakeup-interrupt-controller { |
| compatible = "samsung,exynos4210-wakeup-eint"; |
| interrupt-parent = <&gic>; |
| interrupts = <0 32 0>; |
| }; |
| }; |
| |
| pinctrl_2: pinctrl@03860000 { |
| compatible = "samsung,exynos4210-pinctrl"; |
| reg = <0x03860000 0x1000>; |
| }; |
| |
| tmu: tmu@100C0000 { |
| compatible = "samsung,exynos4210-tmu"; |
| interrupt-parent = <&combiner>; |
| reg = <0x100C0000 0x100>; |
| interrupts = <2 4>; |
| clocks = <&clock CLK_TMU_APBIF>; |
| clock-names = "tmu_apbif"; |
| samsung,tmu_gain = <15>; |
| samsung,tmu_reference_voltage = <7>; |
| status = "disabled"; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <0>; |
| polling-delay = <0>; |
| thermal-sensors = <&tmu 0>; |
| |
| trips { |
| cpu_alert0: cpu-alert-0 { |
| temperature = <85000>; /* millicelsius */ |
| }; |
| cpu_alert1: cpu-alert-1 { |
| temperature = <100000>; /* millicelsius */ |
| }; |
| cpu_alert2: cpu-alert-2 { |
| temperature = <110000>; /* millicelsius */ |
| }; |
| }; |
| }; |
| }; |
| |
| g2d: g2d@12800000 { |
| compatible = "samsung,s5pv210-g2d"; |
| reg = <0x12800000 0x1000>; |
| interrupts = <0 89 0>; |
| clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; |
| clock-names = "sclk_fimg2d", "fimg2d"; |
| power-domains = <&pd_lcd0>; |
| iommus = <&sysmmu_g2d>; |
| }; |
| |
| camera { |
| clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, |
| <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; |
| clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; |
| |
| fimc_0: fimc@11800000 { |
| samsung,pix-limits = <4224 8192 1920 4224>; |
| samsung,mainscaler-ext; |
| samsung,cam-if; |
| }; |
| |
| fimc_1: fimc@11810000 { |
| samsung,pix-limits = <4224 8192 1920 4224>; |
| samsung,mainscaler-ext; |
| samsung,cam-if; |
| }; |
| |
| fimc_2: fimc@11820000 { |
| samsung,pix-limits = <4224 8192 1920 4224>; |
| samsung,mainscaler-ext; |
| samsung,lcd-wb; |
| }; |
| |
| fimc_3: fimc@11830000 { |
| samsung,pix-limits = <1920 8192 1366 1920>; |
| samsung,rotators = <0>; |
| samsung,mainscaler-ext; |
| samsung,lcd-wb; |
| }; |
| }; |
| |
| mixer: mixer@12C10000 { |
| clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer", |
| "sclk_mixer"; |
| clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, |
| <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>, |
| <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>; |
| }; |
| |
| ppmu_lcd1: ppmu_lcd1@12240000 { |
| compatible = "samsung,exynos-ppmu"; |
| reg = <0x12240000 0x2000>; |
| clocks = <&clock CLK_PPMULCD1>; |
| clock-names = "ppmu"; |
| status = "disabled"; |
| }; |
| |
| sysmmu_g2d: sysmmu@12A20000 { |
| compatible = "samsung,exynos-sysmmu"; |
| reg = <0x12A20000 0x1000>; |
| interrupt-parent = <&combiner>; |
| interrupts = <4 7>; |
| clock-names = "sysmmu", "master"; |
| clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; |
| power-domains = <&pd_lcd0>; |
| #iommu-cells = <0>; |
| }; |
| |
| sysmmu_fimd1: sysmmu@12220000 { |
| compatible = "samsung,exynos-sysmmu"; |
| interrupt-parent = <&combiner>; |
| reg = <0x12220000 0x1000>; |
| interrupts = <5 3>; |
| clock-names = "sysmmu", "master"; |
| clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>; |
| power-domains = <&pd_lcd1>; |
| #iommu-cells = <0>; |
| }; |
| |
| bus_dmc: bus_dmc { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_DIV_DMC>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_dmc_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_acp: bus_acp { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_DIV_ACP>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_acp_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_peri: bus_peri { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_ACLK100>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_peri_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_fsys: bus_fsys { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_ACLK133>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_fsys_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_display: bus_display { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_ACLK160>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_display_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_lcd0: bus_lcd0 { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_ACLK200>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_leftbus_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_leftbus: bus_leftbus { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_DIV_GDL>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_leftbus_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_rightbus: bus_rightbus { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_DIV_GDR>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_leftbus_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_mfc: bus_mfc { |
| compatible = "samsung,exynos-bus"; |
| clocks = <&clock CLK_SCLK_MFC>; |
| clock-names = "bus"; |
| operating-points-v2 = <&bus_leftbus_opp_table>; |
| status = "disabled"; |
| }; |
| |
| bus_dmc_opp_table: opp_table1 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp@134000000 { |
| opp-hz = /bits/ 64 <134000000>; |
| opp-microvolt = <1025000>; |
| }; |
| opp@267000000 { |
| opp-hz = /bits/ 64 <267000000>; |
| opp-microvolt = <1050000>; |
| }; |
| opp@400000000 { |
| opp-hz = /bits/ 64 <400000000>; |
| opp-microvolt = <1150000>; |
| }; |
| }; |
| |
| bus_acp_opp_table: opp_table2 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp@134000000 { |
| opp-hz = /bits/ 64 <134000000>; |
| }; |
| opp@160000000 { |
| opp-hz = /bits/ 64 <160000000>; |
| }; |
| opp@200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| }; |
| }; |
| |
| bus_peri_opp_table: opp_table3 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp@5000000 { |
| opp-hz = /bits/ 64 <5000000>; |
| }; |
| opp@100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| }; |
| |
| bus_fsys_opp_table: opp_table4 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp@10000000 { |
| opp-hz = /bits/ 64 <10000000>; |
| }; |
| opp@134000000 { |
| opp-hz = /bits/ 64 <134000000>; |
| }; |
| }; |
| |
| bus_display_opp_table: opp_table5 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp@100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| opp@134000000 { |
| opp-hz = /bits/ 64 <134000000>; |
| }; |
| opp@160000000 { |
| opp-hz = /bits/ 64 <160000000>; |
| }; |
| }; |
| |
| bus_leftbus_opp_table: opp_table6 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp@100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| opp@160000000 { |
| opp-hz = /bits/ 64 <160000000>; |
| }; |
| opp@200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| }; |
| }; |
| }; |
| |
| &gic { |
| cpu-offset = <0x8000>; |
| }; |
| |
| &combiner { |
| samsung,combiner-nr = <16>; |
| interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, |
| <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, |
| <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, |
| <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; |
| }; |
| |
| &mdma1 { |
| power-domains = <&pd_lcd0>; |
| }; |
| |
| &pmu_system_controller { |
| clock-names = "clkout0", "clkout1", "clkout2", "clkout3", |
| "clkout4", "clkout8", "clkout9"; |
| clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, |
| <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, |
| <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; |
| #clock-cells = <1>; |
| }; |
| |
| &rotator { |
| power-domains = <&pd_lcd0>; |
| }; |
| |
| &sysmmu_rotator { |
| power-domains = <&pd_lcd0>; |
| }; |
