Documentation/devicetree/bindings/arm/coresight.txt - linux - Git at Google

 * CoreSight Components:

 CoreSight components are compliant with the ARM CoreSight architecture
 specification and can be connected in various topologies to suit a particular
 SoCs tracing needs. These trace components can generally be classified as
 sinks, links and sources. Trace data produced by one or more sources flows
 through the intermediate links connecting the source to the currently selected
 sink. Each CoreSight component device should use these properties to describe
 its hardware characteristcs.

 * Required properties for all components *except* non-configurable replicators:

 	* compatible: These have to be supplemented with "arm,primecell" as
 	  drivers are using the AMBA bus interface.  Possible values include:
 		- Embedded Trace Buffer (version 1.0):
 			"arm,coresight-etb10", "arm,primecell";

 		- Trace Port Interface Unit:
 			"arm,coresight-tpiu", "arm,primecell";

 		- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
 		  Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
 		  configuration.  The configuration mode (ETB, ETF, ETR) is
 		  discovered at boot time when the device is probed.
 			"arm,coresight-tmc", "arm,primecell";

 		- Trace Funnel:
 			"arm,coresight-funnel", "arm,primecell";

 		- Embedded Trace Macrocell (version 3.x) and
 					Program Flow Trace Macrocell:
 			"arm,coresight-etm3x", "arm,primecell";

 		- Embedded Trace Macrocell (version 4.x):
 			"arm,coresight-etm4x", "arm,primecell";

 		- Coresight programmable Replicator :
 			"arm,coresight-dynamic-replicator", "arm,primecell";

 		- System Trace Macrocell:
 			"arm,coresight-stm", "arm,primecell"; [1]
 		- Coresight Address Translation Unit (CATU)
 			"arm,coresight-catu", "arm,primecell";

 	* reg: physical base address and length of the register
 	  set(s) of the component.

 	* clocks: the clocks associated to this component.

 	* clock-names: the name of the clocks referenced by the code.
 	  Since we are using the AMBA framework, the name of the clock
 	  providing the interconnect should be "apb_pclk", and some
 	  coresight blocks also have an additional clock "atclk", which
 	  clocks the core of that coresight component. The latter clock
 	  is optional.

 	* port or ports: see "Graph bindings for Coresight" below.

 * Additional required properties for System Trace Macrocells (STM):
 	* reg: along with the physical base address and length of the register
 	  set as described above, another entry is required to describe the
 	  mapping of the extended stimulus port area.

 	* reg-names: the only acceptable values are "stm-base" and
 	  "stm-stimulus-base", each corresponding to the areas defined in "reg".

 * Required properties for devices that don't show up on the AMBA bus, such as
   non-configurable replicators:

 	* compatible: Currently supported value is (note the absence of the
 	  AMBA markee):
 		- "arm,coresight-replicator"

 	* port or ports: see "Graph bindings for Coresight" below.

 * Optional properties for ETM/PTMs:

 	* arm,cp14: must be present if the system accesses ETM/PTM management
 	  registers via co-processor 14.

 	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
 	  source is considered to belong to CPU0.

 * Optional property for TMC:

 	* arm,buffer-size: size of contiguous buffer space for TMC ETR
 	  (embedded trace router). This property is obsolete. The buffer size
 	  can be configured dynamically via buffer_size property in sysfs.

 	* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
 	  use the SG mode on this system.

 * Optional property for CATU :
 	* interrupts : Exactly one SPI may be listed for reporting the address
 	  error

 Graph bindings for Coresight
 -------------------------------

 Coresight components are interconnected to create a data path for the flow of
 trace data generated from the "sources" to their collection points "sink".
 Each coresight component must describe the "input" and "output" connections.
 The connections must be described via generic DT graph bindings as described
 by the "bindings/graph.txt", where each "port" along with an "endpoint"
 component represents a hardware port and the connection.

  * All output ports must be listed inside a child node named "out-ports"
  * All input ports must be listed inside a child node named "in-ports".
  * Port address must match the hardware port number.

 Example:

 1. Sinks
 	etb@20010000 {
 		compatible = "arm,coresight-etb10", "arm,primecell";
 		reg = <0 0x20010000 0 0x1000>;

 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		in-ports {
 			port {
 				etb_in_port: endpoint@0 {
 					remote-endpoint = <&replicator_out_port0>;
 				};
 			};
 		};
 	};

 	tpiu@20030000 {
 		compatible = "arm,coresight-tpiu", "arm,primecell";
 		reg = <0 0x20030000 0 0x1000>;

 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		in-ports {
 			port {
 				tpiu_in_port: endpoint@0 {
 					remote-endpoint = <&replicator_out_port1>;
 				};
 			};
 		};
 	};

 	etr@20070000 {
 		compatible = "arm,coresight-tmc", "arm,primecell";
 		reg = <0 0x20070000 0 0x1000>;

 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		in-ports {
 			port {
 				etr_in_port: endpoint {
 					remote-endpoint = <&replicator2_out_port0>;
 				};
 			};
 		};

 		out-ports {
 			port {
 				etr_out_port: endpoint {
 					remote-endpoint = <&catu_in_port>;
 				};
 			};
 		};
 	};

 2. Links
 	replicator {
 		/* non-configurable replicators don't show up on the
 		 * AMBA bus.  As such no need to add "arm,primecell".
 		 */
 		compatible = "arm,coresight-replicator";

 		out-ports {
 			#address-cells = <1>;
 			#size-cells = <0>;

 			/* replicator output ports */
 			port@0 {
 				reg = <0>;
 				replicator_out_port0: endpoint {
 					remote-endpoint = <&etb_in_port>;
 				};
 			};

 			port@1 {
 				reg = <1>;
 				replicator_out_port1: endpoint {
 					remote-endpoint = <&tpiu_in_port>;
 				};
 			};
 		};

 		in-ports {
 			port {
 				replicator_in_port0: endpoint {
 					remote-endpoint = <&funnel_out_port0>;
 				};
 			};
 		};
 	};

 	funnel@20040000 {
 		compatible = "arm,coresight-funnel", "arm,primecell";
 		reg = <0 0x20040000 0 0x1000>;

 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		out-ports {
 			port {
 				funnel_out_port0: endpoint {
 					remote-endpoint =
 							<&replicator_in_port0>;
 				};
 			};
 		};

 		in-ports {
 			#address-cells = <1>;
 			#size-cells = <0>;

 			port@0 {
 				reg = <0>;
 				funnel_in_port0: endpoint {
 					remote-endpoint = <&ptm0_out_port>;
 				};
 			};

 			port@1 {
 				reg = <1>;
 				funnel_in_port1: endpoint {
 					remote-endpoint = <&ptm1_out_port>;
 				};
 			};

 			port@2 {
 				reg = <2>;
 				funnel_in_port2: endpoint {
 					remote-endpoint = <&etm0_out_port>;
 				};
 			};

 		};
 	};

 3. Sources
 	ptm@2201c000 {
 		compatible = "arm,coresight-etm3x", "arm,primecell";
 		reg = <0 0x2201c000 0 0x1000>;

 		cpu = <&cpu0>;
 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		out-ports {
 			port {
 				ptm0_out_port: endpoint {
 					remote-endpoint = <&funnel_in_port0>;
 				};
 			};
 		};
 	};

 	ptm@2201d000 {
 		compatible = "arm,coresight-etm3x", "arm,primecell";
 		reg = <0 0x2201d000 0 0x1000>;

 		cpu = <&cpu1>;
 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";
 		out-ports {
 			port {
 				ptm1_out_port: endpoint {
 					remote-endpoint = <&funnel_in_port1>;
 				};
 			};
 		};
 	};

 4. STM
 	stm@20100000 {
 		compatible = "arm,coresight-stm", "arm,primecell";
 		reg = <0 0x20100000 0 0x1000>,
 		      <0 0x28000000 0 0x180000>;
 		reg-names = "stm-base", "stm-stimulus-base";

 		clocks = <&soc_smc50mhz>;
 		clock-names = "apb_pclk";
 		out-ports {
 			port {
 				stm_out_port: endpoint {
 					remote-endpoint = <&main_funnel_in_port2>;
 				};
 			};
 		};
 	};

 5. CATU

 	catu@207e0000 {
 		compatible = "arm,coresight-catu", "arm,primecell";
 		reg = <0 0x207e0000 0 0x1000>;

 		clocks = <&oscclk6a>;
 		clock-names = "apb_pclk";

 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 		in-ports {
 			port {
 				catu_in_port: endpoint {
 					remote-endpoint = <&etr_out_port>;
 				};
 			};
 		};
 	};

 [1]. There is currently two version of STM: STM32 and STM500.  Both
 have the same HW interface and as such don't need an explicit binding name.
	* CoreSight Components:

	CoreSight components are compliant with the ARM CoreSight architecture
	specification and can be connected in various topologies to suit a particular
	SoCs tracing needs. These trace components can generally be classified as
	sinks, links and sources. Trace data produced by one or more sources flows
	through the intermediate links connecting the source to the currently selected
	sink. Each CoreSight component device should use these properties to describe
	its hardware characteristcs.

	* Required properties for all components except non-configurable replicators:

	* compatible: These have to be supplemented with "arm,primecell" as
	drivers are using the AMBA bus interface. Possible values include:
	- Embedded Trace Buffer (version 1.0):
	"arm,coresight-etb10", "arm,primecell";

	- Trace Port Interface Unit:
	"arm,coresight-tpiu", "arm,primecell";

	- Trace Memory Controller, used for Embedded Trace Buffer(ETB),
	Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
	configuration. The configuration mode (ETB, ETF, ETR) is
	discovered at boot time when the device is probed.
	"arm,coresight-tmc", "arm,primecell";

	- Trace Funnel:
	"arm,coresight-funnel", "arm,primecell";

	- Embedded Trace Macrocell (version 3.x) and
	Program Flow Trace Macrocell:
	"arm,coresight-etm3x", "arm,primecell";

	- Embedded Trace Macrocell (version 4.x):
	"arm,coresight-etm4x", "arm,primecell";

	- Coresight programmable Replicator :
	"arm,coresight-dynamic-replicator", "arm,primecell";

	- System Trace Macrocell:
	"arm,coresight-stm", "arm,primecell"; [1]
	- Coresight Address Translation Unit (CATU)
	"arm,coresight-catu", "arm,primecell";

	* reg: physical base address and length of the register
	set(s) of the component.

	* clocks: the clocks associated to this component.

	* clock-names: the name of the clocks referenced by the code.
	Since we are using the AMBA framework, the name of the clock
	providing the interconnect should be "apb_pclk", and some
	coresight blocks also have an additional clock "atclk", which
	clocks the core of that coresight component. The latter clock
	is optional.

	* port or ports: see "Graph bindings for Coresight" below.

	* Additional required properties for System Trace Macrocells (STM):
	* reg: along with the physical base address and length of the register
	set as described above, another entry is required to describe the
	mapping of the extended stimulus port area.

	* reg-names: the only acceptable values are "stm-base" and
	"stm-stimulus-base", each corresponding to the areas defined in "reg".

	* Required properties for devices that don't show up on the AMBA bus, such as
	non-configurable replicators:

	* compatible: Currently supported value is (note the absence of the
	AMBA markee):
	- "arm,coresight-replicator"

	* port or ports: see "Graph bindings for Coresight" below.

	* Optional properties for ETM/PTMs:

	* arm,cp14: must be present if the system accesses ETM/PTM management
	registers via co-processor 14.

	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
	source is considered to belong to CPU0.

	* Optional property for TMC:

	* arm,buffer-size: size of contiguous buffer space for TMC ETR
	(embedded trace router). This property is obsolete. The buffer size
	can be configured dynamically via buffer_size property in sysfs.

	* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
	use the SG mode on this system.

	* Optional property for CATU :
	* interrupts : Exactly one SPI may be listed for reporting the address
	error

	Graph bindings for Coresight
	-------------------------------

	Coresight components are interconnected to create a data path for the flow of
	trace data generated from the "sources" to their collection points "sink".
	Each coresight component must describe the "input" and "output" connections.
	The connections must be described via generic DT graph bindings as described
	by the "bindings/graph.txt", where each "port" along with an "endpoint"
	component represents a hardware port and the connection.

	* All output ports must be listed inside a child node named "out-ports"
	* All input ports must be listed inside a child node named "in-ports".
	* Port address must match the hardware port number.

	Example:

	1. Sinks
	etb@20010000 {
	compatible = "arm,coresight-etb10", "arm,primecell";
	reg = <0 0x20010000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	in-ports {
	port {
	etb_in_port: endpoint@0 {
	remote-endpoint = <&replicator_out_port0>;
	};
	};
	};
	};

	tpiu@20030000 {
	compatible = "arm,coresight-tpiu", "arm,primecell";
	reg = <0 0x20030000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	in-ports {
	port {
	tpiu_in_port: endpoint@0 {
	remote-endpoint = <&replicator_out_port1>;
	};
	};
	};
	};

	etr@20070000 {
	compatible = "arm,coresight-tmc", "arm,primecell";
	reg = <0 0x20070000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	in-ports {
	port {
	etr_in_port: endpoint {
	remote-endpoint = <&replicator2_out_port0>;
	};
	};
	};

	out-ports {
	port {
	etr_out_port: endpoint {
	remote-endpoint = <&catu_in_port>;
	};
	};
	};
	};

	2. Links
	replicator {
	/* non-configurable replicators don't show up on the
	* AMBA bus. As such no need to add "arm,primecell".
	*/
	compatible = "arm,coresight-replicator";

	out-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/* replicator output ports */
	port@0 {
	reg = <0>;
	replicator_out_port0: endpoint {
	remote-endpoint = <&etb_in_port>;
	};
	};

	port@1 {
	reg = <1>;
	replicator_out_port1: endpoint {
	remote-endpoint = <&tpiu_in_port>;
	};
	};
	};

	in-ports {
	port {
	replicator_in_port0: endpoint {
	remote-endpoint = <&funnel_out_port0>;
	};
	};
	};
	};

	funnel@20040000 {
	compatible = "arm,coresight-funnel", "arm,primecell";
	reg = <0 0x20040000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	funnel_out_port0: endpoint {
	remote-endpoint =
	<&replicator_in_port0>;
	};
	};
	};

	in-ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
	reg = <0>;
	funnel_in_port0: endpoint {
	remote-endpoint = <&ptm0_out_port>;
	};
	};

	port@1 {
	reg = <1>;
	funnel_in_port1: endpoint {
	remote-endpoint = <&ptm1_out_port>;
	};
	};

	port@2 {
	reg = <2>;
	funnel_in_port2: endpoint {
	remote-endpoint = <&etm0_out_port>;
	};
	};

	};
	};

	3. Sources
	ptm@2201c000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0 0x2201c000 0 0x1000>;

	cpu = <&cpu0>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	ptm0_out_port: endpoint {
	remote-endpoint = <&funnel_in_port0>;
	};
	};
	};
	};

	ptm@2201d000 {
	compatible = "arm,coresight-etm3x", "arm,primecell";
	reg = <0 0x2201d000 0 0x1000>;

	cpu = <&cpu1>;
	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	ptm1_out_port: endpoint {
	remote-endpoint = <&funnel_in_port1>;
	};
	};
	};
	};

	4. STM
	stm@20100000 {
	compatible = "arm,coresight-stm", "arm,primecell";
	reg = <0 0x20100000 0 0x1000>,
	<0 0x28000000 0 0x180000>;
	reg-names = "stm-base", "stm-stimulus-base";

	clocks = <&soc_smc50mhz>;
	clock-names = "apb_pclk";
	out-ports {
	port {
	stm_out_port: endpoint {
	remote-endpoint = <&main_funnel_in_port2>;
	};
	};
	};
	};

	5. CATU

	catu@207e0000 {
	compatible = "arm,coresight-catu", "arm,primecell";
	reg = <0 0x207e0000 0 0x1000>;

	clocks = <&oscclk6a>;
	clock-names = "apb_pclk";

	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	in-ports {
	port {
	catu_in_port: endpoint {
	remote-endpoint = <&etr_out_port>;
	};
	};
	};
	};

	[1]. There is currently two version of STM: STM32 and STM500. Both
	have the same HW interface and as such don't need an explicit binding name.