| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Cadence Quad SPI controller |
| |
| maintainers: |
| - Pratyush Yadav <p.yadav@ti.com> |
| |
| allOf: |
| - $ref: spi-controller.yaml# |
| - if: |
| properties: |
| compatible: |
| contains: |
| const: xlnx,versal-ospi-1.0 |
| then: |
| required: |
| - power-domains |
| |
| properties: |
| compatible: |
| oneOf: |
| - items: |
| - enum: |
| - ti,k2g-qspi |
| - ti,am654-ospi |
| - intel,lgm-qspi |
| - xlnx,versal-ospi-1.0 |
| - const: cdns,qspi-nor |
| - const: cdns,qspi-nor |
| |
| reg: |
| items: |
| - description: the controller register set |
| - description: the controller data area |
| |
| interrupts: |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| cdns,fifo-depth: |
| description: |
| Size of the data FIFO in words. |
| $ref: "/schemas/types.yaml#/definitions/uint32" |
| enum: [ 128, 256 ] |
| default: 128 |
| |
| cdns,fifo-width: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| Bus width of the data FIFO in bytes. |
| default: 4 |
| |
| cdns,trigger-address: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| 32-bit indirect AHB trigger address. |
| |
| cdns,is-decoded-cs: |
| type: boolean |
| description: |
| Flag to indicate whether decoder is used to select different chip select |
| for different memory regions. |
| |
| cdns,rclk-en: |
| type: boolean |
| description: |
| Flag to indicate that QSPI return clock is used to latch the read |
| data rather than the QSPI clock. Make sure that QSPI return clock |
| is populated on the board before using this property. |
| |
| power-domains: |
| maxItems: 1 |
| |
| resets: |
| maxItems: 2 |
| |
| reset-names: |
| minItems: 1 |
| maxItems: 2 |
| items: |
| enum: [ qspi, qspi-ocp ] |
| |
| # subnode's properties |
| patternProperties: |
| "@[0-9a-f]+$": |
| type: object |
| description: |
| Flash device uses the below defined properties in the subnode. |
| |
| properties: |
| cdns,read-delay: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| Delay for read capture logic, in clock cycles. |
| |
| cdns,tshsl-ns: |
| description: |
| Delay in nanoseconds for the length that the master mode chip select |
| outputs are de-asserted between transactions. |
| |
| cdns,tsd2d-ns: |
| description: |
| Delay in nanoseconds between one chip select being de-activated |
| and the activation of another. |
| |
| cdns,tchsh-ns: |
| description: |
| Delay in nanoseconds between last bit of current transaction and |
| deasserting the device chip select (qspi_n_ss_out). |
| |
| cdns,tslch-ns: |
| description: |
| Delay in nanoseconds between setting qspi_n_ss_out low and |
| first bit transfer. |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| - cdns,fifo-depth |
| - cdns,fifo-width |
| - cdns,trigger-address |
| - '#address-cells' |
| - '#size-cells' |
| |
| unevaluatedProperties: false |
| |
| examples: |
| - | |
| qspi: spi@ff705000 { |
| compatible = "cdns,qspi-nor"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xff705000 0x1000>, |
| <0xffa00000 0x1000>; |
| interrupts = <0 151 4>; |
| clocks = <&qspi_clk>; |
| cdns,fifo-depth = <128>; |
| cdns,fifo-width = <4>; |
| cdns,trigger-address = <0x00000000>; |
| resets = <&rst 0x1>, <&rst 0x2>; |
| reset-names = "qspi", "qspi-ocp"; |
| |
| flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0x0>; |
| }; |
| }; |