Documentation/devicetree/bindings/mtd/aspeed-smc.txt

* Aspeed Firmware Memory controller
* Aspeed SPI Flash Memory Controller

The Firmware Memory Controller in the Aspeed AST2500 SoC supports
three chip selects, two of which are always of SPI type and the third
can be SPI or NOR type flash. These bindings only describe SPI.

The two SPI flash memory controllers in the AST2500 each support two
chip selects.

Required properties:
  - compatible : Should be one of
	"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
	"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
	"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
	"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers

  - reg : the first contains the control register location and length,
          the second contains the memory window mapping address and length
  - #address-cells : must be 1 corresponding to chip select child binding
  - #size-cells : must be 0 corresponding to chip select child binding

Optional properties:
  - interrupts : Should contain the interrupt for the dma device if an
    FMC

The child nodes are the SPI flash modules which must have a compatible
property as specified in bindings/mtd/jedec,spi-nor.txt

Optionally, the child node can contain properties for SPI mode (may be
ignored):
  - spi-max-frequency - max frequency of spi bus


Example:
fmc: fmc@1e620000 {
	compatible = "aspeed,ast2500-fmc";
	reg = < 0x1e620000 0x94
		0x20000000 0x02000000 >;
	#address-cells = <1>;
	#size-cells = <0>;
	interrupts = <19>;
	flash@0 {
		reg = < 0 >;
		compatible = "jedec,spi-nor";
		/* spi-max-frequency = <>; */
		/* m25p,fast-read; */
		#address-cells = <1>;
		#size-cells = <1>;
	};
};