drivers/thermal/qoriq_thermal.c - linux - Git at Google

 // SPDX-License-Identifier: GPL-2.0
 //
 // Copyright 2016 Freescale Semiconductor, Inc.

 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/sizes.h>
 #include <linux/thermal.h>
 #include <linux/units.h>

 #include "thermal_hwmon.h"

 #define SITES_MAX		16
 #define TMR_DISABLE		0x0
 #define TMR_ME			0x80000000
 #define TMR_ALPF		0x0c000000
 #define TMR_ALPF_V2		0x03000000
 #define TMTMIR_DEFAULT	0x0000000f
 #define TIER_DISABLE	0x0
 #define TEUMR0_V2		0x51009c00
 #define TMSARA_V2		0xe
 #define TMU_VER1		0x1
 #define TMU_VER2		0x2

 #define REGS_TMR	0x000	/* Mode Register */
 #define TMR_DISABLE	0x0
 #define TMR_ME		0x80000000
 #define TMR_ALPF	0x0c000000

 #define REGS_TMTMIR	0x008	/* Temperature measurement interval Register */
 #define TMTMIR_DEFAULT	0x0000000f

 #define REGS_V2_TMSR	0x008	/* monitor site register */

 #define REGS_V2_TMTMIR	0x00c	/* Temperature measurement interval Register */

 #define REGS_TIER	0x020	/* Interrupt Enable Register */
 #define TIER_DISABLE	0x0


 #define REGS_TTCFGR	0x080	/* Temperature Configuration Register */
 #define REGS_TSCFGR	0x084	/* Sensor Configuration Register */

 #define REGS_TRITSR(n)	(0x100 + 16 * (n)) /* Immediate Temperature
 					    * Site Register
 					    */
 #define TRITSR_V	BIT(31)
 #define TRITSR_TP5	BIT(9)
 #define REGS_V2_TMSAR(n)	(0x304 + 16 * (n))	/* TMU monitoring
 						* site adjustment register
 						*/
 #define REGS_TTRnCR(n)	(0xf10 + 4 * (n)) /* Temperature Range n
 					   * Control Register
 					   */
 #define NUM_TTRCR_V1	4
 #define NUM_TTRCR_MAX	16

 #define REGS_IPBRR(n)		(0xbf8 + 4 * (n)) /* IP Block Revision
 						   * Register n
 						   */
 #define REGS_V2_TEUMR(n)	(0xf00 + 4 * (n))

 /*
  * Thermal zone data
  */
 struct qoriq_sensor {
 	int				id;
 };

 struct qoriq_tmu_data {
 	int ver;
 	u32 ttrcr[NUM_TTRCR_MAX];
 	struct regmap *regmap;
 	struct clk *clk;
 	struct qoriq_sensor	sensor[SITES_MAX];
 };

 static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s)
 {
 	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
 }

 static int tmu_get_temp(struct thermal_zone_device *tz, int *temp)
 {
 	struct qoriq_sensor *qsensor = thermal_zone_device_priv(tz);
 	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
 	u32 val;
 	/*
 	 * REGS_TRITSR(id) has the following layout:
 	 *
 	 * For TMU Rev1:
 	 * 31  ... 7 6 5 4 3 2 1 0
 	 *  V          TEMP
 	 *
 	 * Where V bit signifies if the measurement is ready and is
 	 * within sensor range. TEMP is an 8 bit value representing
 	 * temperature in Celsius.

 	 * For TMU Rev2:
 	 * 31  ... 8 7 6 5 4 3 2 1 0
 	 *  V          TEMP
 	 *
 	 * Where V bit signifies if the measurement is ready and is
 	 * within sensor range. TEMP is an 9 bit value representing
 	 * temperature in KelVin.
 	 */

 	regmap_read(qdata->regmap, REGS_TMR, &val);
 	if (!(val & TMR_ME))
 		return -EAGAIN;

 	if (regmap_read_poll_timeout(qdata->regmap,
 				     REGS_TRITSR(qsensor->id),
 				     val,
 				     val & TRITSR_V,
 				     USEC_PER_MSEC,
 				     10 * USEC_PER_MSEC))
 		return -ENODATA;

 	if (qdata->ver == TMU_VER1) {
 		*temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
 	} else {
 		if (val & TRITSR_TP5)
 			*temp = milli_kelvin_to_millicelsius((val & GENMASK(8, 0)) *
 							     MILLIDEGREE_PER_DEGREE + 500);
 		else
 			*temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
 	}

 	return 0;
 }

 static const struct thermal_zone_device_ops tmu_tz_ops = {
 	.get_temp = tmu_get_temp,
 };

 static int qoriq_tmu_register_tmu_zone(struct device *dev,
 				       struct qoriq_tmu_data *qdata)
 {
 	int id, sites = 0;

 	for (id = 0; id < SITES_MAX; id++) {
 		struct thermal_zone_device *tzd;
 		struct qoriq_sensor *sensor = &qdata->sensor[id];
 		int ret;

 		sensor->id = id;

 		tzd = devm_thermal_of_zone_register(dev, id,
 						    sensor,
 						    &tmu_tz_ops);
 		ret = PTR_ERR_OR_ZERO(tzd);
 		if (ret) {
 			if (ret == -ENODEV)
 				continue;

 			return ret;
 		}

 		if (qdata->ver == TMU_VER1)
 			sites |= 0x1 << (15 - id);
 		else
 			sites |= 0x1 << id;

 		devm_thermal_add_hwmon_sysfs(dev, tzd);
 	}

 	if (sites) {
 		if (qdata->ver == TMU_VER1) {
 			regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF | sites);
 		} else {
 			regmap_write(qdata->regmap, REGS_V2_TMSR, sites);
 			regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2);
 		}
 	}

 	return 0;
 }

 static int qoriq_tmu_calibration(struct device *dev,
 				 struct qoriq_tmu_data *data)
 {
 	int i, val, len;
 	const u32 *calibration;
 	struct device_node *np = dev->of_node;

 	len = of_property_count_u32_elems(np, "fsl,tmu-range");
 	if (len < 0 || (data->ver == TMU_VER1 && len > NUM_TTRCR_V1) ||
 	    (data->ver > TMU_VER1 && len > NUM_TTRCR_MAX)) {
 		dev_err(dev, "invalid range data.\n");
 		return len;
 	}

 	val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len);
 	if (val != 0) {
 		dev_err(dev, "failed to read range data.\n");
 		return val;
 	}

 	/* Init temperature range registers */
 	for (i = 0; i < len; i++)
 		regmap_write(data->regmap, REGS_TTRnCR(i), data->ttrcr[i]);

 	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
 	if (calibration == NULL || len % 8) {
 		dev_err(dev, "invalid calibration data.\n");
 		return -ENODEV;
 	}

 	for (i = 0; i < len; i += 8, calibration += 2) {
 		val = of_read_number(calibration, 1);
 		regmap_write(data->regmap, REGS_TTCFGR, val);
 		val = of_read_number(calibration + 1, 1);
 		regmap_write(data->regmap, REGS_TSCFGR, val);
 	}

 	return 0;
 }

 static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
 {
 	/* Disable interrupt, using polling instead */
 	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);

 	/* Set update_interval */

 	if (data->ver == TMU_VER1) {
 		regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
 	} else {
 		regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
 		regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
 	}

 	/* Disable monitoring */
 	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
 }

 static const struct regmap_range qoriq_yes_ranges[] = {
 	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
 	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(15)),
 	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
 	regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
 	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
 	/* Read only registers below */
 	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
 };

 static const struct regmap_access_table qoriq_wr_table = {
 	.yes_ranges	= qoriq_yes_ranges,
 	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges) - 1,
 };

 static const struct regmap_access_table qoriq_rd_table = {
 	.yes_ranges	= qoriq_yes_ranges,
 	.n_yes_ranges	= ARRAY_SIZE(qoriq_yes_ranges),
 };

 static void qoriq_tmu_action(void *p)
 {
 	struct qoriq_tmu_data *data = p;

 	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
 	clk_disable_unprepare(data->clk);
 }

 static int qoriq_tmu_probe(struct platform_device *pdev)
 {
 	int ret;
 	u32 ver;
 	struct qoriq_tmu_data *data;
 	struct device_node *np = pdev->dev.of_node;
 	struct device *dev = &pdev->dev;
 	const bool little_endian = of_property_read_bool(np, "little-endian");
 	const enum regmap_endian format_endian =
 		little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
 	const struct regmap_config regmap_config = {
 		.reg_bits		= 32,
 		.val_bits		= 32,
 		.reg_stride		= 4,
 		.rd_table		= &qoriq_rd_table,
 		.wr_table		= &qoriq_wr_table,
 		.val_format_endian	= format_endian,
 		.max_register		= SZ_4K,
 	};
 	void __iomem *base;

 	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
 			    GFP_KERNEL);
 	if (!data)
 		return -ENOMEM;

 	base = devm_platform_ioremap_resource(pdev, 0);
 	ret = PTR_ERR_OR_ZERO(base);
 	if (ret) {
 		dev_err(dev, "Failed to get memory region\n");
 		return ret;
 	}

 	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
 	ret = PTR_ERR_OR_ZERO(data->regmap);
 	if (ret) {
 		dev_err(dev, "Failed to init regmap (%d)\n", ret);
 		return ret;
 	}

 	data->clk = devm_clk_get_optional(dev, NULL);
 	if (IS_ERR(data->clk))
 		return PTR_ERR(data->clk);

 	ret = clk_prepare_enable(data->clk);
 	if (ret) {
 		dev_err(dev, "Failed to enable clock\n");
 		return ret;
 	}

 	ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
 	if (ret)
 		return ret;

 	/* version register offset at: 0xbf8 on both v1 and v2 */
 	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to read IP block version\n");
 		return ret;
 	}
 	data->ver = (ver >> 8) & 0xff;

 	qoriq_tmu_init_device(data);	/* TMU initialization */

 	ret = qoriq_tmu_calibration(dev, data);	/* TMU calibration */
 	if (ret < 0)
 		return ret;

 	ret = qoriq_tmu_register_tmu_zone(dev, data);
 	if (ret < 0) {
 		dev_err(dev, "Failed to register sensors\n");
 		return ret;
 	}

 	platform_set_drvdata(pdev, data);

 	return 0;
 }

 static int qoriq_tmu_suspend(struct device *dev)
 {
 	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
 	int ret;

 	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
 	if (ret)
 		return ret;

 	clk_disable_unprepare(data->clk);

 	return 0;
 }

 static int qoriq_tmu_resume(struct device *dev)
 {
 	int ret;
 	struct qoriq_tmu_data *data = dev_get_drvdata(dev);

 	ret = clk_prepare_enable(data->clk);
 	if (ret)
 		return ret;

 	/* Enable monitoring */
 	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
 }

 static DEFINE_SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
 				qoriq_tmu_suspend, qoriq_tmu_resume);

 static const struct of_device_id qoriq_tmu_match[] = {
 	{ .compatible = "fsl,qoriq-tmu", },
 	{ .compatible = "fsl,imx8mq-tmu", },
 	{},
 };
 MODULE_DEVICE_TABLE(of, qoriq_tmu_match);

 static struct platform_driver qoriq_tmu = {
 	.driver	= {
 		.name		= "qoriq_thermal",
 		.pm		= pm_sleep_ptr(&qoriq_tmu_pm_ops),
 		.of_match_table	= qoriq_tmu_match,
 	},
 	.probe	= qoriq_tmu_probe,
 };
 module_platform_driver(qoriq_tmu);

 MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
 MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
 MODULE_LICENSE("GPL v2");
	// SPDX-License-Identifier: GPL-2.0
	//
	// Copyright 2016 Freescale Semiconductor, Inc.

	#include <linux/clk.h>
	#include <linux/err.h>
	#include <linux/io.h>
	#include <linux/module.h>
	#include <linux/of.h>
	#include <linux/platform_device.h>
	#include <linux/regmap.h>
	#include <linux/sizes.h>
	#include <linux/thermal.h>
	#include <linux/units.h>

	#include "thermal_hwmon.h"

	#define SITES_MAX 16
	#define TMR_DISABLE 0x0
	#define TMR_ME 0x80000000
	#define TMR_ALPF 0x0c000000
	#define TMR_ALPF_V2 0x03000000
	#define TMTMIR_DEFAULT 0x0000000f
	#define TIER_DISABLE 0x0
	#define TEUMR0_V2 0x51009c00
	#define TMSARA_V2 0xe
	#define TMU_VER1 0x1
	#define TMU_VER2 0x2

	#define REGS_TMR 0x000 /* Mode Register */
	#define TMR_DISABLE 0x0
	#define TMR_ME 0x80000000
	#define TMR_ALPF 0x0c000000

	#define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */
	#define TMTMIR_DEFAULT 0x0000000f

	#define REGS_V2_TMSR 0x008 /* monitor site register */

	#define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */

	#define REGS_TIER 0x020 /* Interrupt Enable Register */
	#define TIER_DISABLE 0x0


	#define REGS_TTCFGR 0x080 /* Temperature Configuration Register */
	#define REGS_TSCFGR 0x084 /* Sensor Configuration Register */

	#define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature
	* Site Register
	*/
	#define TRITSR_V BIT(31)
	#define TRITSR_TP5 BIT(9)
	#define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring
	* site adjustment register
	*/
	#define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
	* Control Register
	*/
	#define NUM_TTRCR_V1 4
	#define NUM_TTRCR_MAX 16

	#define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision
	* Register n
	*/
	#define REGS_V2_TEUMR(n) (0xf00 + 4 * (n))

	/*
	* Thermal zone data
	*/
	struct qoriq_sensor {
	int id;
	};

	struct qoriq_tmu_data {
	int ver;
	u32 ttrcr[NUM_TTRCR_MAX];
	struct regmap *regmap;
	struct clk *clk;
	struct qoriq_sensor sensor[SITES_MAX];
	};

	static struct qoriq_tmu_data qoriq_sensor_to_data(struct qoriq_sensor s)
	{
	return container_of(s, struct qoriq_tmu_data, sensor[s->id]);
	}

	static int tmu_get_temp(struct thermal_zone_device tz, int temp)
	{
	struct qoriq_sensor *qsensor = thermal_zone_device_priv(tz);
	struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor);
	u32 val;
	/*
	* REGS_TRITSR(id) has the following layout:
	*
	* For TMU Rev1:
	* 31 ... 7 6 5 4 3 2 1 0
	* V TEMP
	*
	* Where V bit signifies if the measurement is ready and is
	* within sensor range. TEMP is an 8 bit value representing
	* temperature in Celsius.

	* For TMU Rev2:
	* 31 ... 8 7 6 5 4 3 2 1 0
	* V TEMP
	*
	* Where V bit signifies if the measurement is ready and is
	* within sensor range. TEMP is an 9 bit value representing
	* temperature in KelVin.
	*/

	regmap_read(qdata->regmap, REGS_TMR, &val);
	if (!(val & TMR_ME))
	return -EAGAIN;

	if (regmap_read_poll_timeout(qdata->regmap,
	REGS_TRITSR(qsensor->id),
	val,
	val & TRITSR_V,
	USEC_PER_MSEC,
	10 * USEC_PER_MSEC))
	return -ENODATA;

	if (qdata->ver == TMU_VER1) {
	temp = (val & GENMASK(7, 0)) MILLIDEGREE_PER_DEGREE;
	} else {
	if (val & TRITSR_TP5)
	temp = milli_kelvin_to_millicelsius((val & GENMASK(8, 0))
	MILLIDEGREE_PER_DEGREE + 500);
	else
	*temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
	}

	return 0;
	}

	static const struct thermal_zone_device_ops tmu_tz_ops = {
	.get_temp = tmu_get_temp,
	};

	static int qoriq_tmu_register_tmu_zone(struct device *dev,
	struct qoriq_tmu_data *qdata)
	{
	int id, sites = 0;

	for (id = 0; id < SITES_MAX; id++) {
	struct thermal_zone_device *tzd;
	struct qoriq_sensor *sensor = &qdata->sensor[id];
	int ret;

	sensor->id = id;

	tzd = devm_thermal_of_zone_register(dev, id,
	sensor,
	&tmu_tz_ops);
	ret = PTR_ERR_OR_ZERO(tzd);
	if (ret) {
	if (ret == -ENODEV)
	continue;

	return ret;
	}

	if (qdata->ver == TMU_VER1)
	sites \|= 0x1 << (15 - id);
	else
	sites \|= 0x1 << id;

	devm_thermal_add_hwmon_sysfs(dev, tzd);
	}

	if (sites) {
	if (qdata->ver == TMU_VER1) {
	regmap_write(qdata->regmap, REGS_TMR, TMR_ME \| TMR_ALPF \| sites);
	} else {
	regmap_write(qdata->regmap, REGS_V2_TMSR, sites);
	regmap_write(qdata->regmap, REGS_TMR, TMR_ME \| TMR_ALPF_V2);
	}
	}

	return 0;
	}

	static int qoriq_tmu_calibration(struct device *dev,
	struct qoriq_tmu_data *data)
	{
	int i, val, len;
	const u32 *calibration;
	struct device_node *np = dev->of_node;

	len = of_property_count_u32_elems(np, "fsl,tmu-range");
	if (len < 0 \|\| (data->ver == TMU_VER1 && len > NUM_TTRCR_V1) \|\|
	(data->ver > TMU_VER1 && len > NUM_TTRCR_MAX)) {
	dev_err(dev, "invalid range data.\n");
	return len;
	}

	val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len);
	if (val != 0) {
	dev_err(dev, "failed to read range data.\n");
	return val;
	}

	/* Init temperature range registers */
	for (i = 0; i < len; i++)
	regmap_write(data->regmap, REGS_TTRnCR(i), data->ttrcr[i]);

	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
	if (calibration == NULL \|\| len % 8) {
	dev_err(dev, "invalid calibration data.\n");
	return -ENODEV;
	}

	for (i = 0; i < len; i += 8, calibration += 2) {
	val = of_read_number(calibration, 1);
	regmap_write(data->regmap, REGS_TTCFGR, val);
	val = of_read_number(calibration + 1, 1);
	regmap_write(data->regmap, REGS_TSCFGR, val);
	}

	return 0;
	}

	static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
	{
	/* Disable interrupt, using polling instead */
	regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);

	/* Set update_interval */

	if (data->ver == TMU_VER1) {
	regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT);
	} else {
	regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
	regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
	}

	/* Disable monitoring */
	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
	}

	static const struct regmap_range qoriq_yes_ranges[] = {
	regmap_reg_range(REGS_TMR, REGS_TSCFGR),
	regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(15)),
	regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
	regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
	regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
	/* Read only registers below */
	regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
	};

	static const struct regmap_access_table qoriq_wr_table = {
	.yes_ranges = qoriq_yes_ranges,
	.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1,
	};

	static const struct regmap_access_table qoriq_rd_table = {
	.yes_ranges = qoriq_yes_ranges,
	.n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges),
	};

	static void qoriq_tmu_action(void *p)
	{
	struct qoriq_tmu_data *data = p;

	regmap_write(data->regmap, REGS_TMR, TMR_DISABLE);
	clk_disable_unprepare(data->clk);
	}

	static int qoriq_tmu_probe(struct platform_device *pdev)
	{
	int ret;
	u32 ver;
	struct qoriq_tmu_data *data;
	struct device_node *np = pdev->dev.of_node;
	struct device *dev = &pdev->dev;
	const bool little_endian = of_property_read_bool(np, "little-endian");
	const enum regmap_endian format_endian =
	little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG;
	const struct regmap_config regmap_config = {
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
	.rd_table = &qoriq_rd_table,
	.wr_table = &qoriq_wr_table,
	.val_format_endian = format_endian,
	.max_register = SZ_4K,
	};
	void __iomem *base;

	data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data),
	GFP_KERNEL);
	if (!data)
	return -ENOMEM;

	base = devm_platform_ioremap_resource(pdev, 0);
	ret = PTR_ERR_OR_ZERO(base);
	if (ret) {
	dev_err(dev, "Failed to get memory region\n");
	return ret;
	}

	data->regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
	ret = PTR_ERR_OR_ZERO(data->regmap);
	if (ret) {
	dev_err(dev, "Failed to init regmap (%d)\n", ret);
	return ret;
	}

	data->clk = devm_clk_get_optional(dev, NULL);
	if (IS_ERR(data->clk))
	return PTR_ERR(data->clk);

	ret = clk_prepare_enable(data->clk);
	if (ret) {
	dev_err(dev, "Failed to enable clock\n");
	return ret;
	}

	ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data);
	if (ret)
	return ret;

	/* version register offset at: 0xbf8 on both v1 and v2 */
	ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver);
	if (ret) {
	dev_err(&pdev->dev, "Failed to read IP block version\n");
	return ret;
	}
	data->ver = (ver >> 8) & 0xff;

	qoriq_tmu_init_device(data); /* TMU initialization */

	ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */
	if (ret < 0)
	return ret;

	ret = qoriq_tmu_register_tmu_zone(dev, data);
	if (ret < 0) {
	dev_err(dev, "Failed to register sensors\n");
	return ret;
	}

	platform_set_drvdata(pdev, data);

	return 0;
	}

	static int qoriq_tmu_suspend(struct device *dev)
	{
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
	int ret;

	ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0);
	if (ret)
	return ret;

	clk_disable_unprepare(data->clk);

	return 0;
	}

	static int qoriq_tmu_resume(struct device *dev)
	{
	int ret;
	struct qoriq_tmu_data *data = dev_get_drvdata(dev);

	ret = clk_prepare_enable(data->clk);
	if (ret)
	return ret;

	/* Enable monitoring */
	return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME);
	}

	static DEFINE_SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
	qoriq_tmu_suspend, qoriq_tmu_resume);

	static const struct of_device_id qoriq_tmu_match[] = {
	{ .compatible = "fsl,qoriq-tmu", },
	{ .compatible = "fsl,imx8mq-tmu", },
	{},
	};
	MODULE_DEVICE_TABLE(of, qoriq_tmu_match);

	static struct platform_driver qoriq_tmu = {
	.driver = {
	.name = "qoriq_thermal",
	.pm = pm_sleep_ptr(&qoriq_tmu_pm_ops),
	.of_match_table = qoriq_tmu_match,
	},
	.probe = qoriq_tmu_probe,
	};
	module_platform_driver(qoriq_tmu);

	MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
	MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
	MODULE_LICENSE("GPL v2");