| [ |
| { |
| "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", |
| "EventCode": "0x2e", |
| "EventName": "LONGEST_LAT_CACHE.MISS", |
| "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", |
| "SampleAfterValue": "200003", |
| "UMask": "0x41" |
| }, |
| { |
| "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", |
| "EventCode": "0x2e", |
| "EventName": "LONGEST_LAT_CACHE.REFERENCE", |
| "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", |
| "SampleAfterValue": "200003", |
| "UMask": "0x4f" |
| }, |
| { |
| "BriefDescription": "Counts the number of load ops retired.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", |
| "PEBS": "1", |
| "SampleAfterValue": "200003", |
| "UMask": "0x81" |
| }, |
| { |
| "BriefDescription": "Counts the number of store ops retired.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.ALL_STORES", |
| "PEBS": "1", |
| "SampleAfterValue": "200003", |
| "UMask": "0x82" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x400", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x80", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x10", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x800", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x100", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x20", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x4", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x200", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x40", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x8", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5" |
| }, |
| { |
| "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x6" |
| } |
| ] |
