Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

Device Tree Bindings for the Arasan SDHCI Controller

  The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
  Only deviations are documented here.

  [1] Documentation/devicetree/bindings/mmc/mmc.txt
  [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
  [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
  [4] Documentation/devicetree/bindings/phy/phy-bindings.txt

Required Properties:
  - compatible: Compatibility string.  One of:
    - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
    - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
    - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
    - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
      For this device it is strongly suggested to include arasan,soc-ctl-syscon.
    - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
	Note: This binding has been deprecated and moved to [5].

  [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt

  - reg: From mmc bindings: Register location and length.
  - clocks: From clock bindings: Handles to clock inputs.
  - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
  - interrupts: Interrupt specifier

Required Properties for "arasan,sdhci-5.1":
  - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
  - phy-names:  MUST be "phy_arasan".

Optional Properties:
  - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
    used to access core corecfg registers.  Offsets of registers in this
    syscon are determined based on the main compatible string for the device.
  - clock-output-names: If specified, this will be the name of the card clock
    which will be exposed by this device.  Required if #clock-cells is
    specified.
  - #clock-cells: If specified this should be the value <0>.  With this property
    in place we will export a clock representing the Card Clock.  This clock
    is expected to be consumed by our PHY.  You must also specify
  - xlnx,fails-without-test-cd: when present, the controller doesn't work when
    the CD line is not connected properly, and the line is not connected
    properly. Test mode can be used to force the controller to function.
  - xlnx,int-clock-stable-broken: when present, the controller always reports
    that the internal clock is stable even when it is not.

Example:
	sdhci@e0100000 {
		compatible = "arasan,sdhci-8.9a";
		reg = <0xe0100000 0x1000>;
		clock-names = "clk_xin", "clk_ahb";
		clocks = <&clkc 21>, <&clkc 32>;
		interrupt-parent = <&gic>;
		interrupts = <0 24 4>;
	} ;

	sdhci@e2800000 {
		compatible = "arasan,sdhci-5.1";
		reg = <0xe2800000 0x1000>;
		clock-names = "clk_xin", "clk_ahb";
		clocks = <&cru 8>, <&cru 18>;
		interrupt-parent = <&gic>;
		interrupts = <0 24 4>;
		phys = <&emmc_phy>;
		phy-names = "phy_arasan";
	} ;

	sdhci: sdhci@fe330000 {
		compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
		reg = <0x0 0xfe330000 0x0 0x10000>;
		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
		clock-names = "clk_xin", "clk_ahb";
		arasan,soc-ctl-syscon = <&grf>;
		assigned-clocks = <&cru SCLK_EMMC>;
		assigned-clock-rates = <200000000>;
		clock-output-names = "emmc_cardclock";
		phys = <&emmc_phy>;
		phy-names = "phy_arasan";
		#clock-cells = <0>;
	};