Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)

maintainers:
  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  - Geert Uytterhoeven <geert+renesas@glider.be>

description: |
  IA55 performs various interrupt controls including synchronization for the external
  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
  interrupts output by each IP. And it notifies the interrupt to the GIC
    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
      stand-up edge detection interrupts)

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

properties:
  compatible:
    items:
      - enum:
          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
          - renesas,r9a07g054-irqc    # RZ/V2L
      - const: renesas,rzg2l-irqc

  '#interrupt-cells':
    description: The first cell should contain external interrupt number (IRQ0-7) and the
                 second cell is used to specify the flag.
    const: 2

  '#address-cells':
    const: 0

  interrupt-controller: true

  reg:
    maxItems: 1

  interrupts:
    maxItems: 41

  clocks:
    maxItems: 2

  clock-names:
    items:
      - const: clk
      - const: pclk

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller
  - reg
  - interrupts
  - clocks
  - clock-names
  - power-domains
  - resets

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/clock/r9a07g044-cpg.h>

    irqc: interrupt-controller@110a0000 {
            compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
            reg = <0x110a0000 0x10000>;
            #interrupt-cells = <2>;
            #address-cells = <0>;
            interrupt-controller;
            interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
                     <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
            clock-names = "clk", "pclk";
            power-domains = <&cpg>;
            resets = <&cpg R9A07G044_IA55_RESETN>;
    };