arch/arm/boot/dts/intel/ixp/intel-ixp43x-kixrp435.dts

// SPDX-License-Identifier: ISC
/*
 * Device Tree file for the Intel KIXRP435 Control Plane
 * processor reference design.
 */

/dts-v1/;

#include "intel-ixp43x.dtsi"
#include "intel-ixp4xx-reference-design.dtsi"
#include <dt-bindings/input/input.h>

/ {
	model = "Intel KIXRP435 Reference Design";
	compatible = "intel,kixrp435", "intel,ixp43x";
	#address-cells = <1>;
	#size-cells = <1>;

	soc {
		bus@c4000000 {
			flash@0,0 {
				compatible = "intel,ixp4xx-flash", "cfi-flash";
				bank-width = <2>;
				/* Enable writes on the expansion bus */
				intel,ixp4xx-eb-write-enable = <1>;
				/* 16 MB of Flash mapped in at CS0 */
				reg = <0 0x00000000 0x1000000>;

				partitions {
					compatible = "redboot-fis";
					/* Eraseblock at 0x0fe0000 */
					fis-index-block = <0x7f>;
				};
			};
		};

		/* CHECKME: ethernet set-up taken from Gateworks Cambria */
		ethernet@c800a000 {
			status = "okay";
			queue-rx = <&qmgr 4>;
			queue-txready = <&qmgr 21>;
			phy-mode = "rgmii";
			phy-handle = <&phy1>;

			mdio {
				#address-cells = <1>;
				#size-cells = <0>;

				phy1: ethernet-phy@1 {
					reg = <1>;
				};

				phy2: ethernet-phy@2 {
					reg = <2>;
				};
			};
		};

		ethernet@c800c000 {
			status = "okay";
			queue-rx = <&qmgr 2>;
			queue-txready = <&qmgr 19>;
			phy-mode = "rgmii";
			phy-handle = <&phy2>;
			intel,npe-handle = <&npe 0>;
		};
	};
};