Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Clock bindings for Freescale i.MX7ULP Peripheral Clock Control (PCC) modules

maintainers:
  - A.s. Dong <aisheng.dong@nxp.com>

description: |
  i.MX7ULP Clock functions are under joint control of the System
  Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
  modules, and Core Mode Controller (CMC)1 blocks

  The clocking scheme provides clear separation between M4 domain
  and A7 domain. Except for a few clock sources shared between two
  domains, such as the System Oscillator clock, the Slow IRC (SIRC),
  and and the Fast IRC clock (FIRCLK), clock sources and clock
  management are separated and contained within each domain.

  M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
  A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.

  Note: this binding doc is only for A7 clock domain.

  The Peripheral Clock Control (PCC) is responsible for clock selection,
  optional division and clock gating mode for peripherals in their
  respected power domain.

  The clock consumer should specify the desired clock by having the clock
  ID in its "clocks" phandle cell.
  See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
  i.MX7ULP clock IDs of each module.

properties:
  compatible:
    enum:
      - fsl,imx7ulp-pcc2
      - fsl,imx7ulp-pcc3

  reg:
    maxItems: 1

  '#clock-cells':
    const: 1

  clocks:
    items:
      - description: nic1 bus clock
      - description: nic1 clock
      - description: ddr clock
      - description: apll pfd2
      - description: apll pfd1
      - description: apll pfd0
      - description: usb pll
      - description: system osc bus clock
      - description: fast internal reference clock bus
      - description: rtc osc
      - description: system pll bus clock

  clock-names:
    items:
      - const: nic1_bus_clk
      - const: nic1_clk
      - const: ddr_clk
      - const: apll_pfd2
      - const: apll_pfd1
      - const: apll_pfd0
      - const: upll
      - const: sosc_bus_clk
      - const: firc_bus_clk
      - const: rosc
      - const: spll_bus_clk

required:
  - compatible
  - reg
  - '#clock-cells'
  - clocks
  - clock-names

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/imx7ulp-clock.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    clock-controller@403f0000 {
        compatible = "fsl,imx7ulp-pcc2";
        reg = <0x403f0000 0x10000>;
        #clock-cells = <1>;
        clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
                 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
                 <&scg1 IMX7ULP_CLK_DDR_DIV>,
                 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
                 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
                 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
                 <&scg1 IMX7ULP_CLK_UPLL>,
                 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
                 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
                 <&scg1 IMX7ULP_CLK_ROSC>,
                 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
         clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
                       "apll_pfd2", "apll_pfd1", "apll_pfd0",
                       "upll", "sosc_bus_clk", "firc_bus_clk",
                       "rosc", "spll_bus_clk";
    };

    mmc@40380000 {
        compatible = "fsl,imx7ulp-usdhc";
        reg = <0x40380000 0x10000>;
        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
                 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
                 <&pcc2 IMX7ULP_CLK_USDHC1>;
        clock-names ="ipg", "ahb", "per";
        bus-width = <4>;
    };