| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: NVIDIA Tegra20 SoC External Memory Controller |
| |
| maintainers: |
| - Dmitry Osipenko <digetx@gmail.com> |
| - Jon Hunter <jonathanh@nvidia.com> |
| - Thierry Reding <thierry.reding@gmail.com> |
| |
| description: | |
| The External Memory Controller (EMC) interfaces with the off-chip SDRAM to |
| service the request stream sent from Memory Controller. The EMC also has |
| various performance-affecting settings beyond the obvious SDRAM configuration |
| parameters and initialization settings. Tegra20 EMC supports multiple JEDEC |
| standard protocols: DDR1, LPDDR2 and DDR2. |
| |
| properties: |
| compatible: |
| const: nvidia,tegra20-emc |
| |
| reg: |
| maxItems: 1 |
| |
| clocks: |
| maxItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| "#address-cells": |
| const: 1 |
| |
| "#size-cells": |
| const: 0 |
| |
| "#interconnect-cells": |
| const: 0 |
| |
| nvidia,memory-controller: |
| $ref: /schemas/types.yaml#/definitions/phandle |
| description: |
| Phandle of the Memory Controller node. |
| |
| power-domains: |
| maxItems: 1 |
| description: |
| Phandle of the SoC "core" power domain. |
| |
| operating-points-v2: |
| description: |
| Should contain freqs and voltages and opp-supported-hw property, which |
| is a bitfield indicating SoC process ID mask. |
| |
| nvidia,use-ram-code: |
| type: boolean |
| description: |
| If present, the emc-tables@ sub-nodes will be addressed. |
| |
| $defs: |
| emc-table: |
| type: object |
| properties: |
| compatible: |
| const: nvidia,tegra20-emc-table |
| |
| clock-frequency: |
| description: |
| Memory clock rate in kHz. |
| minimum: 1000 |
| maximum: 900000 |
| |
| reg: |
| maxItems: 1 |
| description: |
| Either an opaque enumerator to tell different tables apart, or |
| the valid frequency for which the table should be used (in kHz). |
| |
| nvidia,emc-registers: |
| description: |
| EMC timing characterization data. These are the registers |
| (see section "15.4.1 EMC Registers" in the TRM) whose values |
| need to be specified, according to the board documentation. |
| $ref: /schemas/types.yaml#/definitions/uint32-array |
| items: |
| - description: EMC_RC |
| - description: EMC_RFC |
| - description: EMC_RAS |
| - description: EMC_RP |
| - description: EMC_R2W |
| - description: EMC_W2R |
| - description: EMC_R2P |
| - description: EMC_W2P |
| - description: EMC_RD_RCD |
| - description: EMC_WR_RCD |
| - description: EMC_RRD |
| - description: EMC_REXT |
| - description: EMC_WDV |
| - description: EMC_QUSE |
| - description: EMC_QRST |
| - description: EMC_QSAFE |
| - description: EMC_RDV |
| - description: EMC_REFRESH |
| - description: EMC_BURST_REFRESH_NUM |
| - description: EMC_PDEX2WR |
| - description: EMC_PDEX2RD |
| - description: EMC_PCHG2PDEN |
| - description: EMC_ACT2PDEN |
| - description: EMC_AR2PDEN |
| - description: EMC_RW2PDEN |
| - description: EMC_TXSR |
| - description: EMC_TCKE |
| - description: EMC_TFAW |
| - description: EMC_TRPAB |
| - description: EMC_TCLKSTABLE |
| - description: EMC_TCLKSTOP |
| - description: EMC_TREFBW |
| - description: EMC_QUSE_EXTRA |
| - description: EMC_FBIO_CFG6 |
| - description: EMC_ODT_WRITE |
| - description: EMC_ODT_READ |
| - description: EMC_FBIO_CFG5 |
| - description: EMC_CFG_DIG_DLL |
| - description: EMC_DLL_XFORM_DQS |
| - description: EMC_DLL_XFORM_QUSE |
| - description: EMC_ZCAL_REF_CNT |
| - description: EMC_ZCAL_WAIT_CNT |
| - description: EMC_AUTO_CAL_INTERVAL |
| - description: EMC_CFG_CLKTRIM_0 |
| - description: EMC_CFG_CLKTRIM_1 |
| - description: EMC_CFG_CLKTRIM_2 |
| |
| required: |
| - clock-frequency |
| - compatible |
| - reg |
| - nvidia,emc-registers |
| |
| additionalProperties: false |
| |
| patternProperties: |
| "^emc-table@[0-9]+$": |
| $ref: "#/$defs/emc-table" |
| |
| "^emc-tables@[a-z0-9-]+$": |
| type: object |
| properties: |
| reg: |
| maxItems: 1 |
| description: |
| An opaque enumerator to tell different tables apart. |
| |
| nvidia,ram-code: |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| description: |
| Value of RAM_CODE this timing set is used for. |
| |
| "#address-cells": |
| const: 1 |
| |
| "#size-cells": |
| const: 0 |
| |
| patternProperties: |
| "^emc-table@[0-9]+$": |
| $ref: "#/$defs/emc-table" |
| |
| required: |
| - nvidia,ram-code |
| |
| additionalProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - clocks |
| - nvidia,memory-controller |
| - "#interconnect-cells" |
| - operating-points-v2 |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| external-memory-controller@7000f400 { |
| compatible = "nvidia,tegra20-emc"; |
| reg = <0x7000f400 0x400>; |
| interrupts = <0 78 4>; |
| clocks = <&clock_controller 57>; |
| |
| nvidia,memory-controller = <&mc>; |
| operating-points-v2 = <&dvfs_opp_table>; |
| power-domains = <&domain>; |
| |
| #interconnect-cells = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| nvidia,use-ram-code; |
| |
| emc-tables@0 { |
| nvidia,ram-code = <0>; |
| reg = <0>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| emc-table@333000 { |
| reg = <333000>; |
| compatible = "nvidia,tegra20-emc-table"; |
| clock-frequency = <333000>; |
| nvidia,emc-registers = <0x00000018 0x00000033 |
| 0x00000012 0x00000004 0x00000004 0x00000005 |
| 0x00000003 0x0000000c 0x00000006 0x00000006 |
| 0x00000003 0x00000001 0x00000004 0x00000005 |
| 0x00000004 0x00000009 0x0000000d 0x00000bff |
| 0x00000000 0x00000003 0x00000003 0x00000006 |
| 0x00000006 0x00000001 0x00000011 0x000000c8 |
| 0x00000003 0x0000000e 0x00000007 0x00000008 |
| 0x00000002 0x00000000 0x00000000 0x00000002 |
| 0x00000000 0x00000000 0x00000083 0xf0440303 |
| 0x007fe010 0x00001414 0x00000000 0x00000000 |
| 0x00000000 0x00000000 0x00000000 0x00000000>; |
| }; |
| }; |
| }; |
