| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright 2016-2017 |
| * Lukasz Majewski, DENX Software Engineering, lukma@denx.de |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx6q.dtsi" |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/pwm/pwm.h> |
| |
| / { |
| model = "Liebherr (LWN) monitor6 i.MX6 Quad Board"; |
| compatible = "lwn,mccmon6", "fsl,imx6q"; |
| |
| memory@10000000 { |
| device_type = "memory"; |
| reg = <0x10000000 0x80000000>; |
| }; |
| |
| backlight_lvds: backlight { |
| compatible = "pwm-backlight"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_backlight>; |
| pwms = <&pwm2 0 5000000 PWM_POLARITY_INVERTED>; |
| brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 10 11 12 13 14 15 16 17 18 19 |
| 20 21 22 23 24 25 26 27 28 29 |
| 30 31 32 33 34 35 36 37 38 39 |
| 40 41 42 43 44 45 46 47 48 49 |
| 50 51 52 53 54 55 56 57 58 59 |
| 60 61 62 63 64 65 66 67 68 69 |
| 70 71 72 73 74 75 76 77 78 79 |
| 80 81 82 83 84 85 86 87 88 89 |
| 90 91 92 93 94 95 96 97 98 99 |
| 100 101 102 103 104 105 106 107 108 109 |
| 110 111 112 113 114 115 116 117 118 119 |
| 120 121 122 123 124 125 126 127 128 129 |
| 130 131 132 133 134 135 136 137 138 139 |
| 140 141 142 143 144 145 146 147 148 149 |
| 150 151 152 153 154 155 156 157 158 159 |
| 160 161 162 163 164 165 166 167 168 169 |
| 170 171 172 173 174 175 176 177 178 179 |
| 180 181 182 183 184 185 186 187 188 189 |
| 190 191 192 193 194 195 196 197 198 199 |
| 200 201 202 203 204 205 206 207 208 209 |
| 210 211 212 213 214 215 216 217 218 219 |
| 220 221 222 223 224 225 226 227 228 229 |
| 230 231 232 233 234 235 236 237 238 239 |
| 240 241 242 243 244 245 246 247 248 249 |
| 250 251 252 253 254 255>; |
| default-brightness-level = <50>; |
| enable-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_lvds: regulator-lvds { |
| compatible = "regulator-fixed"; |
| regulator-name = "lvds_ppen"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_lvds>; |
| gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| panel-lvds0 { |
| compatible = "innolux,g121x1-l03"; |
| backlight = <&backlight_lvds>; |
| power-supply = <®_lvds>; |
| |
| port { |
| panel_in_lvds0: endpoint { |
| remote-endpoint = <&lvds0_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| &ecspi3 { |
| cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_ecspi3_flwp>; |
| status = "okay"; |
| |
| s25sl032p: flash@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "jedec,spi-nor"; |
| spi-max-frequency = <40000000>; |
| reg = <0>; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet>; |
| phy-mode = "rgmii"; |
| phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; |
| interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, |
| <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| pfuze100: pmic@8 { |
| compatible = "fsl,pfuze100"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1ab { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw1c_reg: sw1c { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3950000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3a { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3b_reg: sw3b { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw4_reg: sw4 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vgen1 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen2_reg: vgen2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen3_reg: vgen3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| vgen4_reg: vgen4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vgen5 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vgen6 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &ldb { |
| status = "okay"; |
| |
| lvds0: lvds-channel@0 { |
| fsl,data-mapping = "spwg"; |
| fsl,data-width = <24>; |
| status = "okay"; |
| |
| port@4 { |
| reg = <4>; |
| |
| lvds0_out: endpoint { |
| remote-endpoint = <&panel_in_lvds0>; |
| }; |
| }; |
| }; |
| }; |
| |
| &pwm2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm2>; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart4>; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; |
| bus-width = <4>; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &weim { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>; |
| ranges = <0 0 0x08000000 0x08000000>; |
| status = "okay"; |
| |
| nor@0,0 { |
| compatible = "cfi-flash"; |
| reg = <0 0 0x02000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| bank-width = <2>; |
| use-advanced-sector-protection; |
| fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000 |
| 0x0000c000 0x1404a38e 0x00000000>; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| |
| pinctrl_backlight: dispgrp { |
| fsl,pins = < |
| /* BLEN_OUT */ |
| MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_ecspi3: ecspi3grp { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 |
| MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 |
| MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 |
| >; |
| }; |
| |
| pinctrl_ecspi3_cs: ecspi3csgrp { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 |
| >; |
| }; |
| |
| pinctrl_ecspi3_flwp: ecspi3flwpgrp { |
| fsl,pins = < |
| MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x80000000 |
| >; |
| }; |
| |
| pinctrl_enet: enetgrp { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 |
| MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 |
| MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 |
| MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
| MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_pwm2: pwm2grp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_reg_lvds: reqlvdsgrp { |
| fsl,pins = < |
| /* LVDS_PPEN_OUT */ |
| MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart4: uart4grp { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 |
| MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 |
| >; |
| }; |
| |
| pinctrl_weim_cs0: weimcs0grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 |
| >; |
| }; |
| |
| pinctrl_weim_nor: weimnorgrp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1 |
| MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1 |
| MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060 |
| MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0 |
| MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0 |
| MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0 |
| MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0 |
| MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0 |
| MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0 |
| MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0 |
| MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0 |
| MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0 |
| MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0 |
| MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0 |
| MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0 |
| MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0 |
| MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0 |
| MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0 |
| MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0 |
| MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1 |
| MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1 |
| MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1 |
| MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1 |
| MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1 |
| MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1 |
| MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1 |
| MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1 |
| MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1 |
| MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1 |
| MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1 |
| MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1 |
| MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1 |
| MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1 |
| MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1 |
| MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1 |
| MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1 |
| MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1 |
| MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1 |
| MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1 |
| MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1 |
| MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1 |
| MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1 |
| MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 |
| >; |
| }; |
| }; |
