| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2 |
| |
| maintainers: |
| - Florian Fainelli <f.fainelli@gmail.com> |
| |
| description: > |
| This interrupt controller hardware is a second level interrupt controller that |
| is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based |
| platforms. It can be found on BCM7xxx products starting with BCM7120. |
| |
| Such an interrupt controller has the following hardware design: |
| |
| - outputs multiple interrupts signals towards its interrupt controller parent |
| |
| - controls how some of the interrupts will be flowing, whether they will |
| directly output an interrupt signal towards the interrupt controller parent, |
| or if they will output an interrupt signal at this 2nd level interrupt |
| controller, in particular for UARTs |
| |
| - has one 32-bit enable word and one 32-bit status word |
| |
| - no atomic set/clear operations |
| |
| - not all bits within the interrupt controller actually map to an interrupt |
| |
| The typical hardware layout for this controller is represented below: |
| |
| 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC) |
| |
| 0 -----[ MUX ] ------------|==========> GIC interrupt 75 |
| \-----------\ |
| | |
| 1 -----[ MUX ] --------)---|==========> GIC interrupt 76 |
| \------------| |
| | |
| 2 -----[ MUX ] --------)---|==========> GIC interrupt 77 |
| \------------| |
| | |
| 3 ---------------------| |
| 4 ---------------------| |
| 5 ---------------------| |
| 7 ---------------------|---|===========> GIC interrupt 66 |
| 9 ---------------------| |
| 10 --------------------| |
| 11 --------------------/ |
| |
| 6 ------------------------\ |
| |===========> GIC interrupt 64 |
| 8 ------------------------/ |
| |
| 12 ........................ X |
| 13 ........................ X (not connected) |
| .. |
| 31 ........................ X |
| |
| The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms |
| on many BCM338x/BCM63xx chipsets. It has the following properties: |
| |
| - outputs a single interrupt signal to its interrupt controller parent |
| |
| - contains one or more enable/status word pairs, which often appear at |
| different offsets in different blocks |
| |
| - no atomic set/clear operations |
| |
| allOf: |
| - $ref: /schemas/interrupt-controller.yaml# |
| |
| properties: |
| compatible: |
| items: |
| - enum: |
| - brcm,bcm7120-l2-intc |
| - brcm,bcm3380-l2-intc |
| |
| reg: |
| minItems: 1 |
| maxItems: 4 |
| description: > |
| Specifies the base physical address and size of the registers |
| |
| interrupt-controller: true |
| |
| "#interrupt-cells": |
| const: 1 |
| |
| interrupts: |
| minItems: 1 |
| maxItems: 32 |
| |
| brcm,int-map-mask: |
| $ref: /schemas/types.yaml#/definitions/uint32-array |
| description: > |
| 32-bits bit mask describing how many and which interrupts are wired to |
| this 2nd level interrupt controller, and how they match their respective |
| interrupt parents. Should match exactly the number of interrupts |
| specified in the 'interrupts' property. |
| |
| brcm,irq-can-wake: |
| type: boolean |
| description: > |
| If present, this means the L2 controller can be used as a wakeup source |
| for system suspend/resume. |
| |
| brcm,int-fwd-mask: |
| $ref: /schemas/types.yaml#/definitions/uint32-array |
| maxItems: 1 |
| description: > |
| if present, a bit mask to configure the interrupts which have a mux gate, |
| typically UARTs. Setting these bits will make their respective interrupt |
| outputs bypass this 2nd level interrupt controller completely; it is |
| completely transparent for the interrupt controller parent. This should |
| have one 32-bit word per enable/status pair. |
| |
| additionalProperties: false |
| |
| required: |
| - compatible |
| - reg |
| - interrupt-controller |
| - "#interrupt-cells" |
| - interrupts |
| |
| examples: |
| - | |
| irq0_intc: interrupt-controller@f0406800 { |
| compatible = "brcm,bcm7120-l2-intc"; |
| interrupt-parent = <&intc>; |
| #interrupt-cells = <1>; |
| reg = <0xf0406800 0x8>; |
| interrupt-controller; |
| interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>; |
| brcm,int-map-mask = <0xeb8>, <0x140>; |
| brcm,int-fwd-mask = <0x7>; |
| }; |
| |
| - | |
| irq1_intc: interrupt-controller@10000020 { |
| compatible = "brcm,bcm3380-l2-intc"; |
| reg = <0x10000024 0x4>, <0x1000002c 0x4>, |
| <0x10000020 0x4>, <0x10000028 0x4>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| interrupt-parent = <&cpu_intc>; |
| interrupts = <2>; |
| }; |