| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (C) 2021 MediaTek Inc. |
| * Author: Sam.Shih <sam.shih@mediatek.com> |
| */ |
| |
| /dts-v1/; |
| #include "mt7986a.dtsi" |
| |
| / { |
| model = "MediaTek MT7986a RFB"; |
| compatible = "mediatek,mt7986a-rfb"; |
| |
| aliases { |
| serial0 = &uart0; |
| }; |
| |
| chosen { |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0 0x40000000 0 0x40000000>; |
| }; |
| }; |
| |
| ð { |
| status = "okay"; |
| |
| gmac0: mac@0 { |
| compatible = "mediatek,eth-mac"; |
| reg = <0>; |
| phy-mode = "2500base-x"; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| |
| mdio: mdio-bus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| &mdio { |
| switch: switch@0 { |
| compatible = "mediatek,mt7531"; |
| reg = <31>; |
| reset-gpios = <&pio 5 0>; |
| }; |
| }; |
| |
| &switch { |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| label = "lan0"; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| label = "lan1"; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| label = "lan2"; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| label = "lan3"; |
| }; |
| |
| port@4 { |
| reg = <4>; |
| label = "lan4"; |
| }; |
| |
| port@6 { |
| reg = <6>; |
| label = "cpu"; |
| ethernet = <&gmac0>; |
| phy-mode = "2500base-x"; |
| |
| fixed-link { |
| speed = <2500>; |
| full-duplex; |
| pause; |
| }; |
| }; |
| }; |
| }; |
| |
| &uart0 { |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart1_pins>; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart2_pins>; |
| status = "okay"; |
| }; |
| |
| &pio { |
| uart1_pins: uart1-pins { |
| mux { |
| function = "uart"; |
| groups = "uart1"; |
| }; |
| }; |
| |
| uart2_pins: uart2-pins { |
| mux { |
| function = "uart"; |
| groups = "uart2"; |
| }; |
| }; |
| }; |