arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 NXP
 * Copyright (c) 2019 Engicam srl
 * Copyright (c) 2020 Amarula Solutions(India)
 */

/dts-v1/;

#include "imx8mp.dtsi"
#include "imx8mp-icore-mx8mp.dtsi"
#include <dt-bindings/usb/pd.h>

/ {
	model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit";
	compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp",
		     "fsl,imx8mp";

	chosen {
		stdout-path = &uart2;
	};

	reg_usb1_vbus: regulator-usb1 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usb1>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "usb1_host_vbus";
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "VSD_3V3";
	};
};

/* Ethernet */
&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-handle = <&ethphy0>;
	phy-mode = "rgmii-id";
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@7 {
			compatible = "ethernet-phy-ieee802.3-c22";
			micrel,led-mode = <0>;
			reg = <7>;
		};
	};
};

/* console */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usb3_phy0 {
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "host";
	status = "okay";
};

&usb3_phy1 {
	status = "okay";
};

&usb3_1 {
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

/* SDCARD */
&usdhc2 {
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	pinctrl-names = "default" ;
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&iomuxc {
	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0			0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1			0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2			0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3			0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL			0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0			0x16
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1			0x16
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2			0x16
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3			0x16
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL			0x16
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07				0x10
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x40
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x40
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX	0x140
			MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX	0x140
			MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS	0x140
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
		>;
	};

	pinctrl_reg_usb1: regusb1grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14	0x10
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
		>;
	};
};