| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2020 PHYTEC Messtechnik GmbH |
| * Author: Teresa Remmet <t.remmet@phytec.de> |
| */ |
| |
| #include <dt-bindings/net/ti-dp83867.h> |
| #include "imx8mp.dtsi" |
| |
| / { |
| model = "PHYTEC phyCORE-i.MX8MP"; |
| compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp"; |
| |
| aliases { |
| rtc0 = &rv3028; |
| rtc1 = &snvs_rtc; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0x0 0x40000000 0 0x80000000>; |
| }; |
| |
| reg_vdd_io: regulator-vdd-io { |
| compatible = "regulator-fixed"; |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "VDD_IO"; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| /* ethernet 1 */ |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec>; |
| phy-handle = <ðphy1>; |
| phy-mode = "rgmii-id"; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy1: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| enet-phy-lane-no-swap; |
| ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,min-output-impedance; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| }; |
| }; |
| }; |
| |
| &flexspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexspi0>; |
| status = "okay"; |
| |
| som_flash: flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <80000000>; |
| spi-rx-bus-width = <4>; |
| spi-tx-bus-width = <1>; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| pmic: pmic@25 { |
| compatible = "nxp,pca9450c"; |
| reg = <0x25>; |
| interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-parent = <&gpio4>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic>; |
| |
| regulators { |
| buck1: BUCK1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1000000>; |
| regulator-min-microvolt = <805000>; |
| regulator-name = "VDD_SOC (BUCK1)"; |
| regulator-ramp-delay = <3125>; |
| }; |
| |
| buck2: BUCK2 { |
| nxp,dvs-run-voltage = <950000>; |
| nxp,dvs-standby-voltage = <850000>; |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1050000>; |
| regulator-min-microvolt = <805000>; |
| regulator-name = "VDD_ARM (BUCK2)"; |
| regulator-ramp-delay = <3125>; |
| }; |
| |
| buck4: BUCK4 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <3300000>; |
| regulator-name = "VDD_3V3 (BUCK4)"; |
| }; |
| |
| buck5: BUCK5 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1800000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "VDD_1V8 (BUCK5)"; |
| }; |
| |
| buck6: BUCK6 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1155000>; |
| regulator-min-microvolt = <1045000>; |
| regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; |
| }; |
| |
| ldo1: LDO1 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1950000>; |
| regulator-min-microvolt = <1710000>; |
| regulator-name = "NVCC_SNVS_1V8 (LDO1)"; |
| }; |
| |
| ldo3: LDO3 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <1800000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "VDDA_1V8 (LDO3)"; |
| }; |
| |
| ldo5: LDO5 { |
| regulator-always-on; |
| regulator-boot-on; |
| regulator-max-microvolt = <3300000>; |
| regulator-min-microvolt = <1800000>; |
| regulator-name = "NVCC_SD2 (LDO5)"; |
| }; |
| }; |
| }; |
| |
| eeprom@51 { |
| compatible = "atmel,24c32"; |
| reg = <0x51>; |
| pagesize = <32>; |
| vcc-supply = <®_vdd_io>; |
| }; |
| |
| rv3028: rtc@52 { |
| compatible = "microcrystal,rv3028"; |
| reg = <0x52>; |
| }; |
| }; |
| |
| /* eMMC */ |
| &usdhc3 { |
| assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; |
| assigned-clock-rates = <400000000>; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &gpio1 { |
| gpio-line-names = "", "", "X_PMIC_WDOG_B", "", |
| "", "", "", "", "", "", |
| "", "", "", "", "", "X_nETHPHY_INT"; |
| }; |
| |
| &gpio4 { |
| gpio-line-names = "", "", "", "", |
| "", "", "", "", "", "", |
| "", "", "", "", "", "", |
| "", "", "X_PMIC_IRQ_B"; |
| }; |
| |
| &iomuxc { |
| pinctrl_fec: fecgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 |
| MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 |
| MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 |
| MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 |
| MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 |
| MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 |
| MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 |
| MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 |
| MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 |
| MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 |
| MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 |
| MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 |
| MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 |
| MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 |
| >; |
| }; |
| |
| pinctrl_flexspi0: flexspi0grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 |
| MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 |
| MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 |
| MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 |
| MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 |
| MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 |
| MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1gpiogrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 |
| MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 |
| >; |
| }; |
| |
| pinctrl_pmic: pmicirqgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 |
| MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 |
| MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 |
| MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 |
| MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 |
| MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 |
| MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 |
| MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 |
| MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 |
| MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 |
| MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 |
| MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 |
| MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 |
| MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 |
| MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 |
| MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 |
| MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 |
| MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 |
| MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 |
| MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 |
| MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 |
| MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 |
| MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 |
| MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 |
| MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6 |
| >; |
| }; |
| }; |
