| /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ |
| /* |
| * Copyright 2024 NXP |
| */ |
| |
| #ifndef __IMX95_POWER_H__ |
| #define __IMX95_POWER_H__ |
| |
| #define IMX95_PD_ANA 0 |
| #define IMX95_PD_AON 1 |
| #define IMX95_PD_BBSM 2 |
| #define IMX95_PD_CAMERA 3 |
| #define IMX95_PD_CCMSRCGPC 4 |
| #define IMX95_PD_A55C0 5 |
| #define IMX95_PD_A55C1 6 |
| #define IMX95_PD_A55C2 7 |
| #define IMX95_PD_A55C3 8 |
| #define IMX95_PD_A55C4 9 |
| #define IMX95_PD_A55C5 10 |
| #define IMX95_PD_A55P 11 |
| #define IMX95_PD_DDR 12 |
| #define IMX95_PD_DISPLAY 13 |
| #define IMX95_PD_GPU 14 |
| #define IMX95_PD_HSIO_TOP 15 |
| #define IMX95_PD_HSIO_WAON 16 |
| #define IMX95_PD_M7 17 |
| #define IMX95_PD_NETC 18 |
| #define IMX95_PD_NOC 19 |
| #define IMX95_PD_NPU 20 |
| #define IMX95_PD_VPU 21 |
| #define IMX95_PD_WAKEUP 22 |
| |
| #define IMX95_PERF_ELE 0 |
| #define IMX95_PERF_M33 1 |
| #define IMX95_PERF_WAKEUP 2 |
| #define IMX95_PERF_M7 3 |
| #define IMX95_PERF_DRAM 4 |
| #define IMX95_PERF_HSIO 5 |
| #define IMX95_PERF_NPU 6 |
| #define IMX95_PERF_NOC 7 |
| #define IMX95_PERF_A55 8 |
| #define IMX95_PERF_GPU 9 |
| #define IMX95_PERF_VPU 10 |
| #define IMX95_PERF_CAM 11 |
| #define IMX95_PERF_DISP 12 |
| |
| #endif |
