| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * DTS File for HiSilicon Hi3798cv200 SoC. |
| * |
| * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. |
| */ |
| |
| #include <dt-bindings/clock/histb-clock.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/reset/ti-syscon.h> |
| |
| / { |
| compatible = "hisilicon,hi3798cv200"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| d-cache-size = <0x8000>; /* 32 KiB */ |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| i-cache-size = <0x8000>; /* 32 KiB */ |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu@1 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| d-cache-size = <0x8000>; /* 32 KiB */ |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| i-cache-size = <0x8000>; /* 32 KiB */ |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu@2 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| d-cache-size = <0x8000>; /* 32 KiB */ |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| i-cache-size = <0x8000>; /* 32 KiB */ |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| next-level-cache = <&L2>; |
| }; |
| |
| cpu@3 { |
| compatible = "arm,cortex-a53"; |
| device_type = "cpu"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| d-cache-size = <0x8000>; /* 32 KiB */ |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| i-cache-size = <0x8000>; /* 32 KiB */ |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| next-level-cache = <&L2>; |
| }; |
| }; |
| |
| L2: l2-cache { |
| compatible = "cache"; |
| cache-unified; |
| cache-size = <0x80000>; /* 512 KiB */ |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| cache-level = <2>; |
| }; |
| |
| gic: interrupt-controller@f1001000 { |
| compatible = "arm,gic-400"; |
| reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ |
| <0x0 0xf1002000 0x0 0x2000>, /* GICC */ |
| <0x0 0xf1004000 0x0 0x2000>, /* GICH */ |
| <0x0 0xf1006000 0x0 0x2000>; /* GICV */ |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| #address-cells = <0>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| soc: soc@f0000000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0xf0000000 0x10000000>; |
| |
| crg: clock-reset-controller@8a22000 { |
| compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; |
| reg = <0x8a22000 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <2>; |
| |
| gmacphyrst: reset-controller { |
| compatible = "ti,syscon-reset"; |
| #reset-cells = <1>; |
| ti,reset-bits = < |
| 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) |
| 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) |
| >; |
| }; |
| }; |
| |
| sysctrl: system-controller@8000000 { |
| compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; |
| reg = <0x8000000 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <2>; |
| }; |
| |
| perictrl: peripheral-controller@8a20000 { |
| compatible = "hisilicon,hi3798cv200-perictrl", "syscon", |
| "simple-mfd"; |
| reg = <0x8a20000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x8a20000 0x1000>; |
| |
| usb2_phy1: usb2_phy@120 { |
| compatible = "hisilicon,hi3798cv200-usb2-phy"; |
| reg = <0x120 0x4>; |
| clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; |
| resets = <&crg 0xbc 4>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| usb2_phy1_port0: phy@0 { |
| reg = <0>; |
| #phy-cells = <0>; |
| resets = <&crg 0xbc 8>; |
| }; |
| |
| usb2_phy1_port1: phy@1 { |
| reg = <1>; |
| #phy-cells = <0>; |
| resets = <&crg 0xbc 9>; |
| }; |
| }; |
| |
| usb2_phy2: usb2_phy@124 { |
| compatible = "hisilicon,hi3798cv200-usb2-phy"; |
| reg = <0x124 0x4>; |
| clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; |
| resets = <&crg 0xbc 6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| usb2_phy2_port0: phy@0 { |
| reg = <0>; |
| #phy-cells = <0>; |
| resets = <&crg 0xbc 10>; |
| }; |
| }; |
| |
| combphy0: phy@850 { |
| compatible = "hisilicon,hi3798cv200-combphy"; |
| reg = <0x850 0x8>; |
| #phy-cells = <1>; |
| clocks = <&crg HISTB_COMBPHY0_CLK>; |
| resets = <&crg 0x188 4>; |
| assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; |
| assigned-clock-rates = <100000000>; |
| hisilicon,fixed-mode = <PHY_TYPE_USB3>; |
| }; |
| |
| combphy1: phy@858 { |
| compatible = "hisilicon,hi3798cv200-combphy"; |
| reg = <0x858 0x8>; |
| #phy-cells = <1>; |
| clocks = <&crg HISTB_COMBPHY1_CLK>; |
| resets = <&crg 0x188 12>; |
| assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; |
| assigned-clock-rates = <100000000>; |
| hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; |
| }; |
| }; |
| |
| pmx0: pinconf@8a21000 { |
| compatible = "pinconf-single"; |
| reg = <0x8a21000 0x180>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <7>; |
| pinctrl-single,gpio-range = < |
| &range 0 8 2 /* GPIO 0 */ |
| &range 8 1 0 /* GPIO 1 */ |
| &range 9 4 2 |
| &range 13 1 0 |
| &range 14 1 1 |
| &range 15 1 0 |
| &range 16 5 0 /* GPIO 2 */ |
| &range 21 3 1 |
| &range 24 4 1 /* GPIO 3 */ |
| &range 28 2 2 |
| &range 86 1 1 |
| &range 87 1 0 |
| &range 30 4 2 /* GPIO 4 */ |
| &range 34 3 0 |
| &range 37 1 2 |
| &range 38 3 2 /* GPIO 6 */ |
| &range 41 5 0 |
| &range 46 8 1 /* GPIO 7 */ |
| &range 54 8 1 /* GPIO 8 */ |
| &range 64 7 1 /* GPIO 9 */ |
| &range 71 1 0 |
| &range 72 6 1 /* GPIO 10 */ |
| &range 78 1 0 |
| &range 79 1 1 |
| &range 80 6 1 /* GPIO 11 */ |
| &range 70 2 1 |
| &range 88 8 0 /* GPIO 12 */ |
| >; |
| |
| range: gpio-range { |
| #pinctrl-single,gpio-range-cells = <3>; |
| }; |
| }; |
| |
| uart0: serial@8b00000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x8b00000 0x1000>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@8b02000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| reg = <0x8b02000 0x1000>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; |
| clock-names = "uartclk", "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@8b10000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0x8b10000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; |
| clocks = <&crg HISTB_I2C0_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@8b11000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0x8b11000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; |
| clocks = <&crg HISTB_I2C1_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@8b12000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0x8b12000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; |
| clocks = <&crg HISTB_I2C2_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@8b13000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0x8b13000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; |
| clocks = <&crg HISTB_I2C3_CLK>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@8b14000 { |
| compatible = "hisilicon,hix5hd2-i2c"; |
| reg = <0x8b14000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
| clock-frequency = <400000>; |
| clocks = <&crg HISTB_I2C4_CLK>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@8b1a000 { |
| compatible = "arm,pl022", "arm,primecell"; |
| reg = <0x8b1a000 0x1000>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| num-cs = <1>; |
| cs-gpios = <&gpio7 1 0>; |
| clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>; |
| clock-names = "sspclk", "apb_pclk"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| sd0: mmc@9820000 { |
| compatible = "snps,dw-mshc"; |
| reg = <0x9820000 0x10000>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_SDIO0_BIU_CLK>, |
| <&crg HISTB_SDIO0_CIU_CLK>; |
| clock-names = "biu", "ciu"; |
| resets = <&crg 0x9c 4>; |
| reset-names = "reset"; |
| status = "disabled"; |
| }; |
| |
| emmc: mmc@9830000 { |
| compatible = "hisilicon,hi3798cv200-dw-mshc"; |
| reg = <0x9830000 0x10000>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_MMC_CIU_CLK>, |
| <&crg HISTB_MMC_BIU_CLK>, |
| <&crg HISTB_MMC_SAMPLE_CLK>, |
| <&crg HISTB_MMC_DRV_CLK>; |
| clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; |
| resets = <&crg 0xa0 4>; |
| reset-names = "reset"; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@8b20000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b20000 0x1000>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 0 8>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio1: gpio@8b21000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b21000 0x1000>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = < |
| &pmx0 0 8 1 |
| &pmx0 1 9 4 |
| &pmx0 5 13 1 |
| &pmx0 6 14 1 |
| &pmx0 7 15 1 |
| >; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio2: gpio@8b22000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b22000 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio3: gpio@8b23000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b23000 0x1000>; |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = < |
| &pmx0 0 24 4 |
| &pmx0 4 28 2 |
| &pmx0 6 86 1 |
| &pmx0 7 87 1 |
| >; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio4: gpio@8b24000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b24000 0x1000>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio5: gpio@8004000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8004000 0x1000>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio6: gpio@8b26000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b26000 0x1000>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio7: gpio@8b27000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b27000 0x1000>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 46 8>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio8: gpio@8b28000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b28000 0x1000>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 54 8>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio9: gpio@8b29000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b29000 0x1000>; |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio10: gpio@8b2a000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b2a000 0x1000>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio11: gpio@8b2b000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b2b000 0x1000>; |
| interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gpio12: gpio@8b2c000 { |
| compatible = "arm,pl061", "arm,primecell"; |
| reg = <0x8b2c000 0x1000>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&pmx0 0 88 8>; |
| clocks = <&crg HISTB_APB_CLK>; |
| clock-names = "apb_pclk"; |
| status = "disabled"; |
| }; |
| |
| gmac0: ethernet@9840000 { |
| compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; |
| reg = <0x9840000 0x1000>, |
| <0x984300c 0x4>; |
| interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_ETH0_MAC_CLK>, |
| <&crg HISTB_ETH0_MACIF_CLK>; |
| clock-names = "mac_core", "mac_ifc"; |
| resets = <&crg 0xcc 8>, |
| <&crg 0xcc 10>, |
| <&gmacphyrst 0>; |
| reset-names = "mac_core", "mac_ifc", "phy"; |
| status = "disabled"; |
| }; |
| |
| gmac1: ethernet@9841000 { |
| compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; |
| reg = <0x9841000 0x1000>, |
| <0x9843010 0x4>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_ETH1_MAC_CLK>, |
| <&crg HISTB_ETH1_MACIF_CLK>; |
| clock-names = "mac_core", "mac_ifc"; |
| resets = <&crg 0xcc 9>, |
| <&crg 0xcc 11>, |
| <&gmacphyrst 1>; |
| reset-names = "mac_core", "mac_ifc", "phy"; |
| status = "disabled"; |
| }; |
| |
| ir: ir@8001000 { |
| compatible = "hisilicon,hix5hd2-ir"; |
| reg = <0x8001000 0x1000>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&sysctrl HISTB_IR_CLK>; |
| status = "disabled"; |
| }; |
| |
| pcie: pcie@9860000 { |
| compatible = "hisilicon,hi3798cv200-pcie"; |
| reg = <0x9860000 0x1000>, |
| <0x0 0x2000>, |
| <0x2000000 0x01000000>; |
| reg-names = "control", "rc-dbi", "config"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| bus-range = <0x00 0xff>; |
| num-lanes = <1>; |
| ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>, |
| <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; |
| interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_PCIE_AUX_CLK>, |
| <&crg HISTB_PCIE_PIPE_CLK>, |
| <&crg HISTB_PCIE_SYS_CLK>, |
| <&crg HISTB_PCIE_BUS_CLK>; |
| clock-names = "aux", "pipe", "sys", "bus"; |
| resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; |
| reset-names = "soft", "sys", "bus"; |
| phys = <&combphy1 PHY_TYPE_PCIE>; |
| phy-names = "phy"; |
| status = "disabled"; |
| }; |
| |
| ohci: usb@9880000 { |
| compatible = "generic-ohci"; |
| reg = <0x9880000 0x10000>; |
| interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_USB2_BUS_CLK>, |
| <&crg HISTB_USB2_12M_CLK>, |
| <&crg HISTB_USB2_48M_CLK>; |
| clock-names = "bus", "clk12", "clk48"; |
| resets = <&crg 0xb8 12>; |
| reset-names = "bus"; |
| phys = <&usb2_phy1_port0>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| ehci: usb@9890000 { |
| compatible = "generic-ehci"; |
| reg = <0x9890000 0x10000>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&crg HISTB_USB2_BUS_CLK>, |
| <&crg HISTB_USB2_PHY_CLK>, |
| <&crg HISTB_USB2_UTMI_CLK>; |
| clock-names = "bus", "phy", "utmi"; |
| resets = <&crg 0xb8 12>, |
| <&crg 0xb8 16>, |
| <&crg 0xb8 13>; |
| reset-names = "bus", "phy", "utmi"; |
| phys = <&usb2_phy1_port0>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| }; |
| }; |
