| // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| |
| #include <dt-bindings/clock/mediatek,mt7981-clk.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/reset/mt7986-resets.h> |
| |
| / { |
| compatible = "mediatek,mt7981b"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| }; |
| |
| cpu@1 { |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| oscillator-40m { |
| compatible = "fixed-clock"; |
| clock-frequency = <40000000>; |
| clock-output-names = "clkxtal"; |
| #clock-cells = <0>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| ranges; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| gic: interrupt-controller@c000000 { |
| compatible = "arm,gic-v3"; |
| reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| <0 0x0c080000 0 0x200000>; /* GICR */ |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| infracfg: clock-controller@10001000 { |
| compatible = "mediatek,mt7981-infracfg", "syscon"; |
| reg = <0 0x10001000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| topckgen: clock-controller@1001b000 { |
| compatible = "mediatek,mt7981-topckgen", "syscon"; |
| reg = <0 0x1001b000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| watchdog: watchdog@1001c000 { |
| compatible = "mediatek,mt7986-wdt"; |
| reg = <0 0x1001c000 0 0x1000>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| #reset-cells = <1>; |
| }; |
| |
| clock-controller@1001e000 { |
| compatible = "mediatek,mt7981-apmixedsys"; |
| reg = <0 0x1001e000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| pwm@10048000 { |
| compatible = "mediatek,mt7981-pwm"; |
| reg = <0 0x10048000 0 0x1000>; |
| clocks = <&infracfg CLK_INFRA_PWM_STA>, |
| <&infracfg CLK_INFRA_PWM_HCK>, |
| <&infracfg CLK_INFRA_PWM1_CK>, |
| <&infracfg CLK_INFRA_PWM2_CK>, |
| <&infracfg CLK_INFRA_PWM3_CK>; |
| clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; |
| #pwm-cells = <2>; |
| }; |
| |
| serial@11002000 { |
| compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; |
| reg = <0 0x11002000 0 0x100>; |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uart", "wakeup"; |
| clocks = <&infracfg CLK_INFRA_UART0_SEL>, |
| <&infracfg CLK_INFRA_UART0_CK>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| serial@11003000 { |
| compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; |
| reg = <0 0x11003000 0 0x100>; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uart", "wakeup"; |
| clocks = <&infracfg CLK_INFRA_UART1_SEL>, |
| <&infracfg CLK_INFRA_UART1_CK>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| serial@11004000 { |
| compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart"; |
| reg = <0 0x11004000 0 0x100>; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "uart", "wakeup"; |
| clocks = <&infracfg CLK_INFRA_UART2_SEL>, |
| <&infracfg CLK_INFRA_UART2_CK>; |
| clock-names = "baud", "bus"; |
| status = "disabled"; |
| }; |
| |
| i2c@11007000 { |
| compatible = "mediatek,mt7981-i2c"; |
| reg = <0 0x11007000 0 0x1000>, |
| <0 0x10217080 0 0x80>; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&infracfg CLK_INFRA_I2C0_CK>, |
| <&infracfg CLK_INFRA_AP_DMA_CK>, |
| <&infracfg CLK_INFRA_I2C_MCK_CK>, |
| <&infracfg CLK_INFRA_I2C_PCK_CK>; |
| clock-names = "main", "dma", "arb", "pmic"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi@11009000 { |
| compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; |
| reg = <0 0x11009000 0 0x1000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CLK_TOP_CB_M_D2>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI2_CK>, |
| <&infracfg CLK_INFRA_SPI2_HCK_CK>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi@1100a000 { |
| compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; |
| reg = <0 0x1100a000 0 0x1000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CLK_TOP_CB_M_D2>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI0_CK>, |
| <&infracfg CLK_INFRA_SPI0_HCK_CK>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi@1100b000 { |
| compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm"; |
| reg = <0 0x1100b000 0 0x1000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CLK_TOP_CB_M_D2>, |
| <&topckgen CLK_TOP_SPI_SEL>, |
| <&infracfg CLK_INFRA_SPI1_CK>, |
| <&infracfg CLK_INFRA_SPI1_HCK_CK>; |
| clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pio: pinctrl@11d00000 { |
| compatible = "mediatek,mt7981-pinctrl"; |
| reg = <0 0x11d00000 0 0x1000>, |
| <0 0x11c00000 0 0x1000>, |
| <0 0x11c10000 0 0x1000>, |
| <0 0x11d20000 0 0x1000>, |
| <0 0x11e00000 0 0x1000>, |
| <0 0x11e20000 0 0x1000>, |
| <0 0x11f00000 0 0x1000>, |
| <0 0x11f10000 0 0x1000>, |
| <0 0x1000b000 0 0x1000>; |
| reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", |
| "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; |
| interrupt-controller; |
| interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gic>; |
| gpio-ranges = <&pio 0 0 56>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| #interrupt-cells = <2>; |
| }; |
| |
| efuse@11f20000 { |
| compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; |
| reg = <0 0x11f20000 0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| clock-controller@15000000 { |
| compatible = "mediatek,mt7981-ethsys", "syscon"; |
| reg = <0 0x15000000 0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| wifi@18000000 { |
| compatible = "mediatek,mt7981-wmac"; |
| reg = <0 0x18000000 0 0x1000000>, |
| <0 0x10003000 0 0x1000>, |
| <0 0x11d10000 0 0x1000>; |
| interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, |
| <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; |
| clock-names = "mcu", "ap2conn"; |
| resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; |
| reset-names = "consys"; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
