arch/arm64/boot/dts/mediatek/mt7988a.dtsi

// SPDX-License-Identifier: GPL-2.0-only OR MIT

#include <dt-bindings/clock/mediatek,mt7988-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>

/ {
	compatible = "mediatek,mt7988a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a73";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
		};

		cpu@1 {
			compatible = "arm,cortex-a73";
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
		};

		cpu@2 {
			compatible = "arm,cortex-a73";
			reg = <0x2>;
			device_type = "cpu";
			enable-method = "psci";
		};

		cpu@3 {
			compatible = "arm,cortex-a73";
			reg = <0x3>;
			device_type = "cpu";
			enable-method = "psci";
		};
	};

	oscillator-40m {
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
		#clock-cells = <0>;
		clock-output-names = "clkxtal";
	};

	pmu {
		compatible = "arm,cortex-a73-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	soc {
		compatible = "simple-bus";
		ranges;
		#address-cells = <2>;
		#size-cells = <2>;

		gic: interrupt-controller@c000000 {
			compatible = "arm,gic-v3";
			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
			      <0 0x0c080000 0 0x200000>, /* GICR */
			      <0 0x0c400000 0 0x2000>,   /* GICC */
			      <0 0x0c410000 0 0x1000>,   /* GICH */
			      <0 0x0c420000 0 0x2000>;   /* GICV */
			interrupt-parent = <&gic>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		infracfg: clock-controller@10001000 {
			compatible = "mediatek,mt7988-infracfg", "syscon";
			reg = <0 0x10001000 0 0x1000>;
			#clock-cells = <1>;
		};

		clock-controller@1001b000 {
			compatible = "mediatek,mt7988-topckgen", "syscon";
			reg = <0 0x1001b000 0 0x1000>;
			#clock-cells = <1>;
		};

		watchdog: watchdog@1001c000 {
			compatible = "mediatek,mt7988-wdt";
			reg = <0 0x1001c000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			#reset-cells = <1>;
		};

		clock-controller@1001e000 {
			compatible = "mediatek,mt7988-apmixedsys";
			reg = <0 0x1001e000 0 0x1000>;
			#clock-cells = <1>;
		};

		pwm@10048000 {
			compatible = "mediatek,mt7988-pwm";
			reg = <0 0x10048000 0 0x1000>;
			clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
				 <&infracfg CLK_INFRA_66M_PWM_HCK>,
				 <&infracfg CLK_INFRA_66M_PWM_CK1>,
				 <&infracfg CLK_INFRA_66M_PWM_CK2>,
				 <&infracfg CLK_INFRA_66M_PWM_CK3>,
				 <&infracfg CLK_INFRA_66M_PWM_CK4>,
				 <&infracfg CLK_INFRA_66M_PWM_CK5>,
				 <&infracfg CLK_INFRA_66M_PWM_CK6>,
				 <&infracfg CLK_INFRA_66M_PWM_CK7>,
				 <&infracfg CLK_INFRA_66M_PWM_CK8>;
			clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
				      "pwm4", "pwm5", "pwm6", "pwm7", "pwm8";
			#pwm-cells = <2>;
			status = "disabled";
		};

		i2c@11003000 {
			compatible = "mediatek,mt7981-i2c";
			reg = <0 0x11003000 0 0x1000>,
			      <0 0x10217080 0 0x80>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c@11004000 {
			compatible = "mediatek,mt7981-i2c";
			reg = <0 0x11004000 0 0x1000>,
			      <0 0x10217100 0 0x80>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c@11005000 {
			compatible = "mediatek,mt7981-i2c";
			reg = <0 0x11005000 0 0x1000>,
			      <0 0x10217180 0 0x80>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_I2C_BCK>,
				 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
			clock-names = "main", "dma";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		usb@11190000 {
			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
			reg = <0 0x11190000 0 0x2e00>,
			      <0 0x11193e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_USB_SYS>,
				 <&infracfg CLK_INFRA_USB_REF>,
				 <&infracfg CLK_INFRA_66M_USB_HCK>,
				 <&infracfg CLK_INFRA_133M_USB_HCK>,
				 <&infracfg CLK_INFRA_USB_XHCI>;
			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
		};

		usb@11200000 {
			compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci";
			reg = <0 0x11200000 0 0x2e00>,
			      <0 0x11203e00 0 0x0100>;
			reg-names = "mac", "ippc";
			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
				 <&infracfg CLK_INFRA_USB_CK_P1>,
				 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
				 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>,
				 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>;
			clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
		};

		clock-controller@11f40000 {
			compatible = "mediatek,mt7988-xfi-pll";
			reg = <0 0x11f40000 0 0x1000>;
			resets = <&watchdog 16>;
			#clock-cells = <1>;
		};

		clock-controller@15000000 {
			compatible = "mediatek,mt7988-ethsys", "syscon";
			reg = <0 0x15000000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		clock-controller@15031000 {
			compatible = "mediatek,mt7988-ethwarp";
			reg = <0 0x15031000 0 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
};