| // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| /* |
| * Copyright (c) 2018 MediaTek Inc. |
| * Author: Ben Ho <ben.ho@mediatek.com> |
| * Erin Lo <erin.lo@mediatek.com> |
| */ |
| |
| /dts-v1/; |
| #include "mt8183.dtsi" |
| #include "mt6358.dtsi" |
| |
| / { |
| model = "MediaTek MT8183 evaluation board"; |
| chassis-type = "embedded"; |
| compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; |
| |
| aliases { |
| serial0 = &uart0; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0 0x40000000 0 0x80000000>; |
| }; |
| |
| chosen { |
| stdout-path = "serial0:921600n8"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| scp_mem_reserved: memory@50000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0 0x50000000 0 0x2900000>; |
| no-map; |
| }; |
| }; |
| |
| thermal-sensor { |
| compatible = "murata,ncp03wf104"; |
| pullup-uv = <1800000>; |
| pullup-ohm = <390000>; |
| pulldown-ohm = <0>; |
| io-channels = <&auxadc 0>; |
| }; |
| }; |
| |
| &auxadc { |
| status = "okay"; |
| }; |
| |
| &gpu { |
| mali-supply = <&mt6358_vgpu_reg>; |
| }; |
| |
| &i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c_pins_0>; |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c_pins_1>; |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| &i2c2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c_pins_2>; |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| &i2c3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c_pins_3>; |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| &i2c4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c_pins_4>; |
| status = "okay"; |
| clock-frequency = <1000000>; |
| }; |
| |
| &i2c5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c_pins_5>; |
| status = "okay"; |
| clock-frequency = <1000000>; |
| }; |
| |
| &mmc0 { |
| status = "okay"; |
| pinctrl-names = "default", "state_uhs"; |
| pinctrl-0 = <&mmc0_pins_default>; |
| pinctrl-1 = <&mmc0_pins_uhs>; |
| bus-width = <8>; |
| max-frequency = <200000000>; |
| cap-mmc-highspeed; |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| cap-mmc-hw-reset; |
| no-sdio; |
| no-sd; |
| hs400-ds-delay = <0x12814>; |
| vmmc-supply = <&mt6358_vemc_reg>; |
| vqmmc-supply = <&mt6358_vio18_reg>; |
| assigned-clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>; |
| assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_CK>; |
| non-removable; |
| }; |
| |
| &mmc1 { |
| status = "okay"; |
| pinctrl-names = "default", "state_uhs"; |
| pinctrl-0 = <&mmc1_pins_default>; |
| pinctrl-1 = <&mmc1_pins_uhs>; |
| bus-width = <4>; |
| max-frequency = <200000000>; |
| cap-sd-highspeed; |
| sd-uhs-sdr50; |
| sd-uhs-sdr104; |
| cap-sdio-irq; |
| no-mmc; |
| no-sd; |
| vmmc-supply = <&mt6358_vmch_reg>; |
| vqmmc-supply = <&mt6358_vmc_reg>; |
| keep-power-in-suspend; |
| wakeup-source; |
| non-removable; |
| }; |
| |
| &mt6358_vgpu_reg { |
| regulator-min-microvolt = <625000>; |
| regulator-max-microvolt = <900000>; |
| |
| regulator-coupled-with = <&mt6358_vsram_gpu_reg>; |
| regulator-coupled-max-spread = <100000>; |
| }; |
| |
| &mt6358_vsram_gpu_reg { |
| regulator-min-microvolt = <850000>; |
| regulator-max-microvolt = <1000000>; |
| |
| regulator-coupled-with = <&mt6358_vgpu_reg>; |
| regulator-coupled-max-spread = <100000>; |
| }; |
| |
| &pio { |
| i2c_pins_0: i2c0 { |
| pins_i2c { |
| pinmux = <PINMUX_GPIO82__FUNC_SDA0>, |
| <PINMUX_GPIO83__FUNC_SCL0>; |
| mediatek,pull-up-adv = <3>; |
| }; |
| }; |
| |
| i2c_pins_1: i2c1 { |
| pins_i2c { |
| pinmux = <PINMUX_GPIO81__FUNC_SDA1>, |
| <PINMUX_GPIO84__FUNC_SCL1>; |
| mediatek,pull-up-adv = <3>; |
| }; |
| }; |
| |
| i2c_pins_2: i2c2 { |
| pins_i2c { |
| pinmux = <PINMUX_GPIO103__FUNC_SCL2>, |
| <PINMUX_GPIO104__FUNC_SDA2>; |
| mediatek,pull-up-adv = <3>; |
| }; |
| }; |
| |
| i2c_pins_3: i2c3 { |
| pins_i2c { |
| pinmux = <PINMUX_GPIO50__FUNC_SCL3>, |
| <PINMUX_GPIO51__FUNC_SDA3>; |
| mediatek,pull-up-adv = <3>; |
| }; |
| }; |
| |
| i2c_pins_4: i2c4 { |
| pins_i2c { |
| pinmux = <PINMUX_GPIO105__FUNC_SCL4>, |
| <PINMUX_GPIO106__FUNC_SDA4>; |
| mediatek,pull-up-adv = <3>; |
| }; |
| }; |
| |
| i2c_pins_5: i2c5 { |
| pins_i2c { |
| pinmux = <PINMUX_GPIO48__FUNC_SCL5>, |
| <PINMUX_GPIO49__FUNC_SDA5>; |
| mediatek,pull-up-adv = <3>; |
| }; |
| }; |
| |
| spi_pins_0: spi0 { |
| pins_spi { |
| pinmux = <PINMUX_GPIO85__FUNC_SPI0_MI>, |
| <PINMUX_GPIO86__FUNC_SPI0_CSB>, |
| <PINMUX_GPIO87__FUNC_SPI0_MO>, |
| <PINMUX_GPIO88__FUNC_SPI0_CLK>; |
| bias-disable; |
| }; |
| }; |
| |
| mmc0_pins_default: mmc0default { |
| pins_cmd_dat { |
| pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, |
| <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, |
| <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, |
| <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, |
| <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, |
| <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, |
| <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, |
| <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, |
| <PINMUX_GPIO122__FUNC_MSDC0_CMD>; |
| input-enable; |
| bias-pull-up; |
| }; |
| |
| pins_clk { |
| pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; |
| bias-pull-down; |
| }; |
| |
| pins_rst { |
| pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; |
| bias-pull-up; |
| }; |
| }; |
| |
| mmc0_pins_uhs: mmc0 { |
| pins_cmd_dat { |
| pinmux = <PINMUX_GPIO123__FUNC_MSDC0_DAT0>, |
| <PINMUX_GPIO128__FUNC_MSDC0_DAT1>, |
| <PINMUX_GPIO125__FUNC_MSDC0_DAT2>, |
| <PINMUX_GPIO132__FUNC_MSDC0_DAT3>, |
| <PINMUX_GPIO126__FUNC_MSDC0_DAT4>, |
| <PINMUX_GPIO129__FUNC_MSDC0_DAT5>, |
| <PINMUX_GPIO127__FUNC_MSDC0_DAT6>, |
| <PINMUX_GPIO130__FUNC_MSDC0_DAT7>, |
| <PINMUX_GPIO122__FUNC_MSDC0_CMD>; |
| input-enable; |
| drive-strength = <MTK_DRIVE_10mA>; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
| }; |
| |
| pins_clk { |
| pinmux = <PINMUX_GPIO124__FUNC_MSDC0_CLK>; |
| drive-strength = <MTK_DRIVE_10mA>; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| }; |
| |
| pins_ds { |
| pinmux = <PINMUX_GPIO131__FUNC_MSDC0_DSL>; |
| drive-strength = <MTK_DRIVE_10mA>; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| }; |
| |
| pins_rst { |
| pinmux = <PINMUX_GPIO133__FUNC_MSDC0_RSTB>; |
| drive-strength = <MTK_DRIVE_10mA>; |
| bias-pull-up; |
| }; |
| }; |
| |
| mmc1_pins_default: mmc1default { |
| pins_cmd_dat { |
| pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, |
| <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, |
| <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, |
| <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, |
| <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; |
| input-enable; |
| bias-pull-up; |
| }; |
| |
| pins_clk { |
| pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; |
| input-enable; |
| bias-pull-down; |
| }; |
| |
| pins_pmu { |
| pinmux = <PINMUX_GPIO178__FUNC_GPIO178>, |
| <PINMUX_GPIO166__FUNC_GPIO166>; |
| output-high; |
| }; |
| }; |
| |
| mmc1_pins_uhs: mmc1 { |
| pins_cmd_dat { |
| pinmux = <PINMUX_GPIO31__FUNC_MSDC1_CMD>, |
| <PINMUX_GPIO32__FUNC_MSDC1_DAT0>, |
| <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, |
| <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, |
| <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; |
| drive-strength = <MTK_DRIVE_6mA>; |
| input-enable; |
| bias-pull-up = <MTK_PUPD_SET_R1R0_01>; |
| }; |
| |
| pins_clk { |
| pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; |
| drive-strength = <MTK_DRIVE_6mA>; |
| bias-pull-down = <MTK_PUPD_SET_R1R0_10>; |
| input-enable; |
| }; |
| }; |
| |
| spi_pins_1: spi1 { |
| pins_spi { |
| pinmux = <PINMUX_GPIO161__FUNC_SPI1_A_MI>, |
| <PINMUX_GPIO162__FUNC_SPI1_A_CSB>, |
| <PINMUX_GPIO163__FUNC_SPI1_A_MO>, |
| <PINMUX_GPIO164__FUNC_SPI1_A_CLK>; |
| bias-disable; |
| }; |
| }; |
| |
| spi_pins_2: spi2 { |
| pins_spi { |
| pinmux = <PINMUX_GPIO0__FUNC_SPI2_CSB>, |
| <PINMUX_GPIO1__FUNC_SPI2_MO>, |
| <PINMUX_GPIO2__FUNC_SPI2_CLK>, |
| <PINMUX_GPIO94__FUNC_SPI2_MI>; |
| bias-disable; |
| }; |
| }; |
| |
| spi_pins_3: spi3 { |
| pins_spi { |
| pinmux = <PINMUX_GPIO21__FUNC_SPI3_MI>, |
| <PINMUX_GPIO22__FUNC_SPI3_CSB>, |
| <PINMUX_GPIO23__FUNC_SPI3_MO>, |
| <PINMUX_GPIO24__FUNC_SPI3_CLK>; |
| bias-disable; |
| }; |
| }; |
| |
| spi_pins_4: spi4 { |
| pins_spi { |
| pinmux = <PINMUX_GPIO17__FUNC_SPI4_MI>, |
| <PINMUX_GPIO18__FUNC_SPI4_CSB>, |
| <PINMUX_GPIO19__FUNC_SPI4_MO>, |
| <PINMUX_GPIO20__FUNC_SPI4_CLK>; |
| bias-disable; |
| }; |
| }; |
| |
| spi_pins_5: spi5 { |
| pins_spi { |
| pinmux = <PINMUX_GPIO13__FUNC_SPI5_MI>, |
| <PINMUX_GPIO14__FUNC_SPI5_CSB>, |
| <PINMUX_GPIO15__FUNC_SPI5_MO>, |
| <PINMUX_GPIO16__FUNC_SPI5_CLK>; |
| bias-disable; |
| }; |
| }; |
| |
| pwm_pins_1: pwm1 { |
| pins_pwm { |
| pinmux = <PINMUX_GPIO90__FUNC_PWM_A>; |
| }; |
| }; |
| }; |
| |
| &pmic { |
| interrupts-extended = <&pio 182 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| &mfg { |
| domain-supply = <&mt6358_vgpu_reg>; |
| }; |
| |
| &spi0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_pins_0>; |
| mediatek,pad-select = <0>; |
| status = "okay"; |
| }; |
| |
| &spi1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_pins_1>; |
| mediatek,pad-select = <0>; |
| status = "okay"; |
| }; |
| |
| &spi2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_pins_2>; |
| mediatek,pad-select = <0>; |
| status = "okay"; |
| }; |
| |
| &spi3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_pins_3>; |
| mediatek,pad-select = <0>; |
| status = "okay"; |
| }; |
| |
| &spi4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_pins_4>; |
| mediatek,pad-select = <0>; |
| status = "okay"; |
| }; |
| |
| &spi5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi_pins_5>; |
| mediatek,pad-select = <0>; |
| status = "okay"; |
| |
| }; |
| |
| &cci { |
| proc-supply = <&mt6358_vproc12_reg>; |
| }; |
| |
| &cpu0 { |
| proc-supply = <&mt6358_vproc12_reg>; |
| }; |
| |
| &cpu1 { |
| proc-supply = <&mt6358_vproc12_reg>; |
| }; |
| |
| &cpu2 { |
| proc-supply = <&mt6358_vproc12_reg>; |
| }; |
| |
| &cpu3 { |
| proc-supply = <&mt6358_vproc12_reg>; |
| }; |
| |
| &cpu4 { |
| proc-supply = <&mt6358_vproc11_reg>; |
| }; |
| |
| &cpu5 { |
| proc-supply = <&mt6358_vproc11_reg>; |
| }; |
| |
| &cpu6 { |
| proc-supply = <&mt6358_vproc11_reg>; |
| }; |
| |
| &cpu7 { |
| proc-supply = <&mt6358_vproc11_reg>; |
| }; |
| |
| &uart0 { |
| status = "okay"; |
| }; |
| |
| &pwm1 { |
| status = "okay"; |
| pinctrl-0 = <&pwm_pins_1>; |
| pinctrl-names = "default"; |
| }; |
