| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * IPQ5332 device tree source |
| * |
| * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/clock/qcom,apss-ipq.h> |
| #include <dt-bindings/clock/qcom,ipq5332-gcc.h> |
| #include <dt-bindings/interconnect/qcom,ipq5332.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| clocks { |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| |
| xo_board: xo-board-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| operating-points-v2 = <&cpu_opp_table>; |
| }; |
| |
| CPU1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| operating-points-v2 = <&cpu_opp_table>; |
| }; |
| |
| CPU2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x2>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| operating-points-v2 = <&cpu_opp_table>; |
| }; |
| |
| CPU3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x3>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; |
| operating-points-v2 = <&cpu_opp_table>; |
| }; |
| |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-ipq5332", "qcom,scm"; |
| qcom,dload-mode = <&tcsr 0x6100>; |
| }; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0x40000000 0x0 0x0>; |
| }; |
| |
| cpu_opp_table: opp-table-cpu { |
| compatible = "operating-points-v2-kryo-cpu"; |
| opp-shared; |
| nvmem-cells = <&cpu_speed_bin>; |
| |
| opp-1100000000 { |
| opp-hz = /bits/ 64 <1100000000>; |
| opp-supported-hw = <0x7>; |
| clock-latency-ns = <200000>; |
| }; |
| |
| opp-1500000000 { |
| opp-hz = /bits/ 64 <1500000000>; |
| opp-supported-hw = <0x3>; |
| clock-latency-ns = <200000>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| bootloader@4a100000 { |
| reg = <0x0 0x4a100000 0x0 0x400000>; |
| no-map; |
| }; |
| |
| sbl@4a500000 { |
| reg = <0x0 0x4a500000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| tz_mem: tz@4a600000 { |
| reg = <0x0 0x4a600000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| smem@4a800000 { |
| compatible = "qcom,smem"; |
| reg = <0x0 0x4a800000 0x0 0x100000>; |
| no-map; |
| |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| }; |
| |
| soc@0 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| |
| usbphy0: phy@7b000 { |
| compatible = "qcom,ipq5332-usb-hsphy"; |
| reg = <0x0007b000 0x12c>; |
| |
| clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; |
| |
| resets = <&gcc GCC_QUSB2_0_PHY_BCR>; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| qfprom: efuse@a4000 { |
| compatible = "qcom,ipq5332-qfprom", "qcom,qfprom"; |
| reg = <0x000a4000 0x721>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpu_speed_bin: cpu-speed-bin@1d { |
| reg = <0x1d 0x2>; |
| bits = <7 2>; |
| }; |
| }; |
| |
| rng: rng@e3000 { |
| compatible = "qcom,prng-ee"; |
| reg = <0x000e3000 0x1000>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "core"; |
| }; |
| |
| tlmm: pinctrl@1000000 { |
| compatible = "qcom,ipq5332-tlmm"; |
| reg = <0x01000000 0x300000>; |
| interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 53>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| serial_0_pins: serial0-state { |
| pins = "gpio18", "gpio19"; |
| function = "blsp0_uart0"; |
| drive-strength = <8>; |
| bias-pull-up; |
| }; |
| }; |
| |
| gcc: clock-controller@1800000 { |
| compatible = "qcom,ipq5332-gcc"; |
| reg = <0x01800000 0x80000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #interconnect-cells = <1>; |
| clocks = <&xo_board>, |
| <&sleep_clk>, |
| <0>, |
| <0>, |
| <0>; |
| }; |
| |
| tcsr_mutex: hwlock@1905000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x01905000 0x20000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| tcsr: syscon@1937000 { |
| compatible = "qcom,tcsr-ipq5332", "syscon"; |
| reg = <0x01937000 0x21000>; |
| }; |
| |
| sdhc: mmc@7804000 { |
| compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0x07804000 0x1000>, <0x07805000 0x1000>; |
| |
| interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>, |
| <&xo_board>; |
| clock-names = "iface", "core", "xo"; |
| status = "disabled"; |
| }; |
| |
| blsp_dma: dma-controller@7884000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x07884000 0x1d000>; |
| interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| }; |
| |
| blsp1_uart0: serial@78af000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x078af000 0x200>; |
| interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp1_uart1: serial@78b0000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x078b0000 0x200>; |
| interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp_dma 2>, <&blsp_dma 3>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| blsp1_spi0: spi@78b5000 { |
| compatible = "qcom,spi-qup-v2.2.1"; |
| reg = <0x078b5000 0x600>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp_dma 4>, <&blsp_dma 5>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c1: i2c@78b6000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x078b6000 0x600>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp_dma 6>, <&blsp_dma 7>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| blsp1_spi2: spi@78b7000 { |
| compatible = "qcom,spi-qup-v2.2.1"; |
| reg = <0x078b7000 0x600>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp_dma 8>, <&blsp_dma 9>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| usb: usb@8af8800 { |
| compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; |
| reg = <0x08af8800 0x400>; |
| |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "pwr_event", |
| "dp_hs_phy_irq", |
| "dm_hs_phy_irq"; |
| |
| clocks = <&gcc GCC_USB0_MASTER_CLK>, |
| <&gcc GCC_USB0_SLEEP_CLK>, |
| <&gcc GCC_USB0_MOCK_UTMI_CLK>; |
| clock-names = "core", |
| "sleep", |
| "mock_utmi"; |
| |
| resets = <&gcc GCC_USB_BCR>; |
| |
| qcom,select-utmi-as-pipe-clk; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| interconnects = <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>, |
| <&gcc MASTER_SNOC_USB &gcc SLAVE_SNOC_USB>; |
| interconnect-names = "usb-ddr", "apps-usb"; |
| |
| status = "disabled"; |
| |
| usb_dwc: usb@8a00000 { |
| compatible = "snps,dwc3"; |
| reg = <0x08a00000 0xe000>; |
| clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; |
| clock-names = "ref"; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| phy-names = "usb2-phy"; |
| phys = <&usbphy0>; |
| tx-fifo-resize; |
| snps,is-utmi-l1-suspend; |
| snps,hird-threshold = /bits/ 8 <0x0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_u3_susphy_quirk; |
| }; |
| }; |
| |
| intc: interrupt-controller@b000000 { |
| compatible = "qcom,msm-qgic2"; |
| reg = <0x0b000000 0x1000>, /* GICD */ |
| <0x0b002000 0x1000>, /* GICC */ |
| <0x0b001000 0x1000>, /* GICH */ |
| <0x0b004000 0x1000>; /* GICV */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x0b00c000 0x3000>; |
| |
| v2m0: v2m@0 { |
| compatible = "arm,gic-v2m-frame"; |
| reg = <0x00000000 0xffd>; |
| msi-controller; |
| }; |
| |
| v2m1: v2m@1000 { |
| compatible = "arm,gic-v2m-frame"; |
| reg = <0x00001000 0xffd>; |
| msi-controller; |
| }; |
| |
| v2m2: v2m@2000 { |
| compatible = "arm,gic-v2m-frame"; |
| reg = <0x00002000 0xffd>; |
| msi-controller; |
| }; |
| }; |
| |
| watchdog: watchdog@b017000 { |
| compatible = "qcom,apss-wdt-ipq5332", "qcom,kpss-wdt"; |
| reg = <0x0b017000 0x1000>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&sleep_clk>; |
| timeout-sec = <30>; |
| }; |
| |
| apcs_glb: mailbox@b111000 { |
| compatible = "qcom,ipq5332-apcs-apps-global", |
| "qcom,ipq6018-apcs-apps-global"; |
| reg = <0x0b111000 0x1000>; |
| #clock-cells = <1>; |
| clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>; |
| clock-names = "pll", "xo", "gpll0"; |
| #mbox-cells = <1>; |
| }; |
| |
| a53pll: clock@b116000 { |
| compatible = "qcom,ipq5332-a53pll"; |
| reg = <0x0b116000 0x40>; |
| #clock-cells = <0>; |
| clocks = <&xo_board>; |
| clock-names = "xo"; |
| }; |
| |
| timer@b120000 { |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0b120000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| frame@b120000 { |
| reg = <0x0b121000 0x1000>, |
| <0x0b122000 0x1000>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| frame-number = <0>; |
| }; |
| |
| frame@b123000 { |
| reg = <0x0b123000 0x1000>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| frame-number = <1>; |
| status = "disabled"; |
| }; |
| |
| frame@b124000 { |
| reg = <0x0b124000 0x1000>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| frame-number = <2>; |
| status = "disabled"; |
| }; |
| |
| frame@b125000 { |
| reg = <0x0b125000 0x1000>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| frame-number = <3>; |
| status = "disabled"; |
| }; |
| |
| frame@b126000 { |
| reg = <0x0b126000 0x1000>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| frame-number = <4>; |
| status = "disabled"; |
| }; |
| |
| frame@b127000 { |
| reg = <0x0b127000 0x1000>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| frame-number = <5>; |
| status = "disabled"; |
| }; |
| |
| frame@b128000 { |
| reg = <0x0b128000 0x1000>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| frame-number = <6>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| }; |
