| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. |
| */ |
| |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,sm4450-camcc.h> |
| #include <dt-bindings/clock/qcom,sm4450-dispcc.h> |
| #include <dt-bindings/clock/qcom,sm4450-gcc.h> |
| #include <dt-bindings/clock/qcom,sm4450-gpucc.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| chosen { }; |
| |
| clocks { |
| xo_board: xo-board { |
| compatible = "fixed-clock"; |
| clock-frequency = <76800000>; |
| #clock-cells = <0>; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <32000>; |
| #clock-cells = <0>; |
| }; |
| |
| bi_tcxo_div2: bi-tcxo-div2-clk { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-mult = <1>; |
| clock-div = <2>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x0>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_0>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| |
| L3_0: l3-cache { |
| compatible = "cache"; |
| cache-level = <3>; |
| cache-unified; |
| }; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x100>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_100>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| |
| L2_100: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x200>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_200>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| |
| L2_200: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x300>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_300>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| |
| L2_300: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x400>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_400>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| |
| L2_400: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x500>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_500>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| |
| L2_500: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a78"; |
| reg = <0x0 0x600>; |
| clocks = <&cpufreq_hw 1>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_600>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| |
| L2_600: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a78"; |
| reg = <0x0 0x700>; |
| clocks = <&cpufreq_hw 1>; |
| enable-method = "psci"; |
| next-level-cache = <&L2_700>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| |
| L2_700: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| |
| core6 { |
| cpu = <&CPU6>; |
| }; |
| |
| core7 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <800>; |
| exit-latency-us = <750>; |
| min-residency-us = <4090>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <600>; |
| exit-latency-us = <1550>; |
| min-residency-us = <4791>; |
| local-timer-stop; |
| }; |
| }; |
| |
| domain-idle-states { |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "domain-idle-state"; |
| arm,psci-suspend-param = <0x41000044>; |
| entry-latency-us = <1050>; |
| exit-latency-us = <2500>; |
| min-residency-us = <5309>; |
| }; |
| |
| CLUSTER_SLEEP_1: cluster-sleep-1 { |
| compatible = "domain-idle-state"; |
| arm,psci-suspend-param = <0x41003344>; |
| entry-latency-us = <1561>; |
| exit-latency-us = <2801>; |
| min-residency-us = <8550>; |
| }; |
| }; |
| }; |
| |
| memory@a0000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0xa0000000 0x0 0x0>; |
| }; |
| |
| pmu-a55 { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| pmu-a78 { |
| compatible = "arm,cortex-a78-pmu"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| |
| CPU_PD0: power-domain-cpu0 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD1: power-domain-cpu1 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD2: power-domain-cpu2 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD3: power-domain-cpu3 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD4: power-domain-cpu4 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD5: power-domain-cpu5 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD6: power-domain-cpu6 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD7: power-domain-cpu7 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CLUSTER_PD: power-domain-cpu-cluster0 { |
| #power-domain-cells = <0>; |
| domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; |
| }; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| aop_cmd_db_mem: cmd-db@80860000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0x0 0x80860000 0x0 0x20000>; |
| no-map; |
| }; |
| }; |
| |
| soc: soc@0 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0 0x10 0>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,sm4450-gcc"; |
| reg = <0x0 0x00100000 0x0 0x1f4200>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&sleep_clk>, |
| <0>, |
| <0>, |
| <0>, |
| <0>; |
| }; |
| |
| qupv3_id_0: geniqup@ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0x0 0x00ac0000 0x0 0x2000>; |
| ranges; |
| clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| clock-names = "m-ahb", "s-ahb"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| status = "disabled"; |
| |
| uart7: serial@a88000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0x0 0x00a88000 0x0 0x4000>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| }; |
| |
| tcsr_mutex: hwlock@1f40000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x0 0x01f40000 0x0 0x40000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| gpucc: clock-controller@3d90000 { |
| compatible = "qcom,sm4450-gpucc"; |
| reg = <0x0 0x03d90000 0x0 0xa000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_GPU_GPLL0_CLK_SRC>, |
| <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| camcc: clock-controller@ade0000 { |
| compatible = "qcom,sm4450-camcc"; |
| reg = <0x0 0x0ade0000 0x0 0x20000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_CAMERA_AHB_CLK>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| dispcc: clock-controller@af00000 { |
| compatible = "qcom,sm4450-dispcc"; |
| reg = <0x0 0x0af00000 0x0 0x20000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&rpmhcc RPMH_CXO_CLK_A>, |
| <&gcc GCC_DISP_AHB_CLK>, |
| <&sleep_clk>, |
| <0>, |
| <0>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| pdc: interrupt-controller@b220000 { |
| compatible = "qcom,sm4450-pdc", "qcom,pdc"; |
| reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; |
| qcom,pdc-ranges = <0 480 94>, <94 494 31>, |
| <125 63 1>; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| tlmm: pinctrl@f100000 { |
| compatible = "qcom,sm4450-tlmm"; |
| reg = <0x0 0x0f100000 0x0 0x300000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 137>; |
| wakeup-parent = <&pdc>; |
| |
| qup_uart7_rx: qup-uart7-rx-state { |
| pins = "gpio23"; |
| function = "qup1_se2_l2"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| qup_uart7_tx: qup-uart7-tx-state { |
| pins = "gpio22"; |
| function = "qup1_se2_l2"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| |
| intc: interrupt-controller@17200000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ |
| <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| }; |
| |
| timer@17420000 { |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0 0x17420000 0x0 0x1000>; |
| ranges = <0 0 0 0x20000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| frame@17421000 { |
| reg = <0x17421000 0x1000>, |
| <0x17422000 0x1000>; |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| frame@17423000 { |
| reg = <0x17423000 0x1000>; |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| frame@17425000 { |
| reg = <0x17425000 0x1000>; |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| frame@17427000 { |
| reg = <0x17427000 0x1000>; |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| frame@17429000 { |
| reg = <0x17429000 0x1000>; |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| frame@1742b000 { |
| reg = <0x1742b000 0x1000>; |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| frame@1742d000 { |
| reg = <0x1742d000 0x1000>; |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| apps_rsc: rsc@17a00000 { |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0x0 0x17a00000 0x0 0x10000>, |
| <0x0 0x17a10000 0x0 0x10000>, |
| <0x0 0x17a20000 0x0 0x10000>; |
| reg-names = "drv-0", "drv-1", "drv-2"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| label = "apps_rsc"; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, <CONTROL_TCS 0>; |
| power-domains = <&CLUSTER_PD>; |
| |
| apps_bcm_voter: bcm-voter { |
| compatible = "qcom,bcm-voter"; |
| }; |
| |
| rpmhcc: clock-controller { |
| compatible = "qcom,sm4450-rpmh-clk"; |
| #clock-cells = <1>; |
| clocks = <&xo_board>; |
| clock-names = "xo"; |
| }; |
| }; |
| |
| cpufreq_hw: cpufreq@17d91000 { |
| compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss"; |
| reg = <0 0x17d91000 0 0x1000>, |
| <0 0x17d92000 0 0x1000>; |
| reg-names = "freq-domain0", "freq-domain1"; |
| clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; |
| clock-names = "xo", "alternate"; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; |
| #freq-domain-cells = <1>; |
| #clock-cells = <1>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| }; |
