| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd |
| * Copyright (c) 2020 Engicam srl |
| * Copyright (c) 2020 Amarula Solutions(India) |
| */ |
| |
| /dts-v1/; |
| #include "px30.dtsi" |
| #include "px30-engicam-edimm2.2.dtsi" |
| #include "px30-engicam-px30-core.dtsi" |
| |
| / { |
| model = "Engicam PX30.Core EDIMM2.2 Starter Kit"; |
| compatible = "engicam,px30-core-edimm2.2", "engicam,px30-core", |
| "rockchip,px30"; |
| |
| chosen { |
| stdout-path = "serial2:115200n8"; |
| }; |
| }; |
| |
| &pinctrl { |
| bt { |
| bt_enable_h: bt-enable-h { |
| rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; |
| }; |
| }; |
| |
| sdio-pwrseq { |
| wifi_enable_h: wifi-enable-h { |
| rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; |
| }; |
| }; |
| }; |
| |
| &sdio_pwrseq { |
| reset-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; |
| }; |
| |
| &vcc3v3_btreg { |
| enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; |
| }; |
