arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT

#include "rk3568-fastrhino-r66s.dtsi"

/ {
	model = "Lunzn FastRhino R68S";
	compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";

	aliases {
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		mmc0 = &sdhci;
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <&saradc 0>;
		io-channel-names = "buttons";
		keyup-threshold-microvolt = <1800000>;

		button-recovery {
			label = "Recovery";
			linux,code = <KEY_VENDOR>;
			press-threshold-microvolt = <1750>;
		};
	};
};

&gmac0 {
	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-handle = <&rgmii_phy0>;
	phy-mode = "rgmii-id";
	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus>;
	status = "okay";
};

&gmac1 {
	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;
	clock_in_out = "output";
	phy-handle = <&rgmii_phy1>;
	phy-mode = "rgmii-id";
	pinctrl-names = "default";
	pinctrl-0 = <&gmac1m1_miim
		     &gmac1m1_tx_bus2
		     &gmac1m1_rx_bus2
		     &gmac1m1_rgmii_clk
		     &gmac1m1_rgmii_bus>;
	status = "okay";
};

&mdio0 {
	rgmii_phy0: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x1>;
		pinctrl-0 = <&eth_phy0_reset_pin>;
		pinctrl-names = "default";
		reset-assert-us = <20000>;
		reset-deassert-us = <100000>;
		reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
	};
};

&mdio1 {
	rgmii_phy1: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x1>;
		pinctrl-0 = <&eth_phy1_reset_pin>;
		pinctrl-names = "default";
		reset-assert-us = <20000>;
		reset-deassert-us = <100000>;
		reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
	};
};

&pinctrl {
	gmac0 {
		eth_phy0_reset_pin: eth-phy0-reset-pin {
			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	gmac1 {
		eth_phy1_reset_pin: eth-phy1-reset-pin {
			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};

&pmu_io_domains {
	vccio3-supply = <&vcc_3v3>;
};

&sdhci {
	bus-width = <8>;
	max-frequency = <200000000>;
	non-removable;
	pinctrl-names = "default";
	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
	status = "okay";
};