| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2021 Rockchip Electronics Co., Ltd. |
| */ |
| |
| #include <dt-bindings/clock/rk3568-cru.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/phy/phy.h> |
| #include <dt-bindings/pinctrl/rockchip.h> |
| #include <dt-bindings/power/rk3568-power.h> |
| #include <dt-bindings/soc/rockchip,boot-mode.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| gpio0 = &gpio0; |
| gpio1 = &gpio1; |
| gpio2 = &gpio2; |
| gpio3 = &gpio3; |
| gpio4 = &gpio4; |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| serial0 = &uart0; |
| serial1 = &uart1; |
| serial2 = &uart2; |
| serial3 = &uart3; |
| serial4 = &uart4; |
| serial5 = &uart5; |
| serial6 = &uart6; |
| serial7 = &uart7; |
| serial8 = &uart8; |
| serial9 = &uart9; |
| spi0 = &spi0; |
| spi1 = &spi1; |
| spi2 = &spi2; |
| spi3 = &spi3; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x0>; |
| clocks = <&scmi_clk 0>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| operating-points-v2 = <&cpu0_opp_table>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l3_cache>; |
| }; |
| |
| cpu1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x100>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| operating-points-v2 = <&cpu0_opp_table>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l3_cache>; |
| }; |
| |
| cpu2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x200>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| operating-points-v2 = <&cpu0_opp_table>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l3_cache>; |
| }; |
| |
| cpu3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x300>; |
| #cooling-cells = <2>; |
| enable-method = "psci"; |
| operating-points-v2 = <&cpu0_opp_table>; |
| i-cache-size = <0x8000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <128>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <128>; |
| next-level-cache = <&l3_cache>; |
| }; |
| }; |
| |
| /* |
| * There are no private per-core L2 caches, but only the |
| * L3 cache that appears to the CPU cores as L2 caches |
| */ |
| l3_cache: l3-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x80000>; |
| cache-line-size = <64>; |
| cache-sets = <512>; |
| }; |
| |
| cpu0_opp_table: opp-table-0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-408000000 { |
| opp-hz = /bits/ 64 <408000000>; |
| opp-microvolt = <900000 900000 1150000>; |
| clock-latency-ns = <40000>; |
| }; |
| |
| opp-600000000 { |
| opp-hz = /bits/ 64 <600000000>; |
| opp-microvolt = <900000 900000 1150000>; |
| }; |
| |
| opp-816000000 { |
| opp-hz = /bits/ 64 <816000000>; |
| opp-microvolt = <900000 900000 1150000>; |
| opp-suspend; |
| }; |
| |
| opp-1104000000 { |
| opp-hz = /bits/ 64 <1104000000>; |
| opp-microvolt = <900000 900000 1150000>; |
| }; |
| |
| opp-1416000000 { |
| opp-hz = /bits/ 64 <1416000000>; |
| opp-microvolt = <900000 900000 1150000>; |
| }; |
| |
| opp-1608000000 { |
| opp-hz = /bits/ 64 <1608000000>; |
| opp-microvolt = <975000 975000 1150000>; |
| }; |
| |
| opp-1800000000 { |
| opp-hz = /bits/ 64 <1800000000>; |
| opp-microvolt = <1050000 1050000 1150000>; |
| }; |
| }; |
| |
| display_subsystem: display-subsystem { |
| compatible = "rockchip,display-subsystem"; |
| ports = <&vop_out>; |
| }; |
| |
| firmware { |
| scmi: scmi { |
| compatible = "arm,scmi-smc"; |
| arm,smc-id = <0x82000010>; |
| shmem = <&scmi_shmem>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| scmi_clk: protocol@14 { |
| reg = <0x14>; |
| #clock-cells = <1>; |
| }; |
| }; |
| }; |
| |
| gpu_opp_table: opp-table-1 { |
| compatible = "operating-points-v2"; |
| |
| opp-200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| opp-microvolt = <850000 850000 1000000>; |
| }; |
| |
| opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-microvolt = <850000 850000 1000000>; |
| }; |
| |
| opp-400000000 { |
| opp-hz = /bits/ 64 <400000000>; |
| opp-microvolt = <850000 850000 1000000>; |
| }; |
| |
| opp-600000000 { |
| opp-hz = /bits/ 64 <600000000>; |
| opp-microvolt = <900000 900000 1000000>; |
| }; |
| |
| opp-700000000 { |
| opp-hz = /bits/ 64 <700000000>; |
| opp-microvolt = <950000 950000 1000000>; |
| }; |
| |
| opp-800000000 { |
| opp-hz = /bits/ 64 <800000000>; |
| opp-microvolt = <1000000 1000000 1000000>; |
| }; |
| }; |
| |
| hdmi_sound: hdmi-sound { |
| compatible = "simple-audio-card"; |
| simple-audio-card,name = "HDMI"; |
| simple-audio-card,format = "i2s"; |
| simple-audio-card,mclk-fs = <256>; |
| status = "disabled"; |
| |
| simple-audio-card,codec { |
| sound-dai = <&hdmi>; |
| }; |
| |
| simple-audio-card,cpu { |
| sound-dai = <&i2s0_8ch>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| arm,no-tick-in-suspend; |
| }; |
| |
| xin24m: xin24m { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "xin24m"; |
| #clock-cells = <0>; |
| }; |
| |
| xin32k: xin32k { |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| clock-output-names = "xin32k"; |
| pinctrl-0 = <&clk32k_out0>; |
| pinctrl-names = "default"; |
| #clock-cells = <0>; |
| }; |
| |
| sram@10f000 { |
| compatible = "mmio-sram"; |
| reg = <0x0 0x0010f000 0x0 0x100>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x0 0x0010f000 0x100>; |
| |
| scmi_shmem: sram@0 { |
| compatible = "arm,scmi-shmem"; |
| reg = <0x0 0x100>; |
| }; |
| }; |
| |
| sata1: sata@fc400000 { |
| compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; |
| reg = <0 0xfc400000 0 0x1000>; |
| clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, |
| <&cru CLK_SATA1_RXOOB>; |
| clock-names = "sata", "pmalive", "rxoob"; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&combphy1 PHY_TYPE_SATA>; |
| phy-names = "sata-phy"; |
| ports-implemented = <0x1>; |
| power-domains = <&power RK3568_PD_PIPE>; |
| status = "disabled"; |
| }; |
| |
| sata2: sata@fc800000 { |
| compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; |
| reg = <0 0xfc800000 0 0x1000>; |
| clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, |
| <&cru CLK_SATA2_RXOOB>; |
| clock-names = "sata", "pmalive", "rxoob"; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&combphy2 PHY_TYPE_SATA>; |
| phy-names = "sata-phy"; |
| ports-implemented = <0x1>; |
| power-domains = <&power RK3568_PD_PIPE>; |
| status = "disabled"; |
| }; |
| |
| usb_host0_xhci: usb@fcc00000 { |
| compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; |
| reg = <0x0 0xfcc00000 0x0 0x400000>; |
| interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, |
| <&cru ACLK_USB3OTG0>; |
| clock-names = "ref_clk", "suspend_clk", |
| "bus_clk"; |
| dr_mode = "otg"; |
| phy_type = "utmi_wide"; |
| power-domains = <&power RK3568_PD_PIPE>; |
| resets = <&cru SRST_USB3OTG0>; |
| snps,dis_u2_susphy_quirk; |
| status = "disabled"; |
| }; |
| |
| usb_host1_xhci: usb@fd000000 { |
| compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; |
| reg = <0x0 0xfd000000 0x0 0x400000>; |
| interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, |
| <&cru ACLK_USB3OTG1>; |
| clock-names = "ref_clk", "suspend_clk", |
| "bus_clk"; |
| dr_mode = "host"; |
| phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| phy_type = "utmi_wide"; |
| power-domains = <&power RK3568_PD_PIPE>; |
| resets = <&cru SRST_USB3OTG1>; |
| snps,dis_u2_susphy_quirk; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@fd400000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ |
| <0x0 0xfd460000 0 0x80000>; /* GICR */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| mbi-alias = <0x0 0xfd410000>; |
| mbi-ranges = <296 24>; |
| msi-controller; |
| }; |
| |
| usb_host0_ehci: usb@fd800000 { |
| compatible = "generic-ehci"; |
| reg = <0x0 0xfd800000 0x0 0x40000>; |
| interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, |
| <&cru PCLK_USB>; |
| phys = <&usb2phy1_otg>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| usb_host0_ohci: usb@fd840000 { |
| compatible = "generic-ohci"; |
| reg = <0x0 0xfd840000 0x0 0x40000>; |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, |
| <&cru PCLK_USB>; |
| phys = <&usb2phy1_otg>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| usb_host1_ehci: usb@fd880000 { |
| compatible = "generic-ehci"; |
| reg = <0x0 0xfd880000 0x0 0x40000>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, |
| <&cru PCLK_USB>; |
| phys = <&usb2phy1_host>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| usb_host1_ohci: usb@fd8c0000 { |
| compatible = "generic-ohci"; |
| reg = <0x0 0xfd8c0000 0x0 0x40000>; |
| interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, |
| <&cru PCLK_USB>; |
| phys = <&usb2phy1_host>; |
| phy-names = "usb"; |
| status = "disabled"; |
| }; |
| |
| pmugrf: syscon@fdc20000 { |
| compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; |
| reg = <0x0 0xfdc20000 0x0 0x10000>; |
| |
| pmu_io_domains: io-domains { |
| compatible = "rockchip,rk3568-pmu-io-voltage-domain"; |
| status = "disabled"; |
| }; |
| }; |
| |
| pipegrf: syscon@fdc50000 { |
| reg = <0x0 0xfdc50000 0x0 0x1000>; |
| }; |
| |
| grf: syscon@fdc60000 { |
| compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; |
| reg = <0x0 0xfdc60000 0x0 0x10000>; |
| }; |
| |
| pipe_phy_grf1: syscon@fdc80000 { |
| compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; |
| reg = <0x0 0xfdc80000 0x0 0x1000>; |
| }; |
| |
| pipe_phy_grf2: syscon@fdc90000 { |
| compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; |
| reg = <0x0 0xfdc90000 0x0 0x1000>; |
| }; |
| |
| usb2phy0_grf: syscon@fdca0000 { |
| compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; |
| reg = <0x0 0xfdca0000 0x0 0x8000>; |
| }; |
| |
| usb2phy1_grf: syscon@fdca8000 { |
| compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; |
| reg = <0x0 0xfdca8000 0x0 0x8000>; |
| }; |
| |
| pmucru: clock-controller@fdd00000 { |
| compatible = "rockchip,rk3568-pmucru"; |
| reg = <0x0 0xfdd00000 0x0 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| cru: clock-controller@fdd20000 { |
| compatible = "rockchip,rk3568-cru"; |
| reg = <0x0 0xfdd20000 0x0 0x1000>; |
| clocks = <&xin24m>; |
| clock-names = "xin24m"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; |
| assigned-clock-rates = <32768>, <1200000000>, <200000000>; |
| assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; |
| rockchip,grf = <&grf>; |
| }; |
| |
| i2c0: i2c@fdd40000 { |
| compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; |
| reg = <0x0 0xfdd40000 0x0 0x1000>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; |
| clock-names = "i2c", "pclk"; |
| pinctrl-0 = <&i2c0_xfer>; |
| pinctrl-names = "default"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@fdd50000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfdd50000 0x0 0x100>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 0>, <&dmac0 1>; |
| pinctrl-0 = <&uart0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| pwm0: pwm@fdd70000 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfdd70000 0x0 0x10>; |
| clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm0m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm1: pwm@fdd70010 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfdd70010 0x0 0x10>; |
| clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm1m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm2: pwm@fdd70020 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfdd70020 0x0 0x10>; |
| clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm2m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm3: pwm@fdd70030 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfdd70030 0x0 0x10>; |
| clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm3_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pmu: power-management@fdd90000 { |
| compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; |
| reg = <0x0 0xfdd90000 0x0 0x1000>; |
| |
| power: power-controller { |
| compatible = "rockchip,rk3568-power-controller"; |
| #power-domain-cells = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* These power domains are grouped by VD_GPU */ |
| power-domain@RK3568_PD_GPU { |
| reg = <RK3568_PD_GPU>; |
| clocks = <&cru ACLK_GPU_PRE>, |
| <&cru PCLK_GPU_PRE>; |
| pm_qos = <&qos_gpu>; |
| #power-domain-cells = <0>; |
| }; |
| |
| /* These power domains are grouped by VD_LOGIC */ |
| power-domain@RK3568_PD_VI { |
| reg = <RK3568_PD_VI>; |
| clocks = <&cru HCLK_VI>, |
| <&cru PCLK_VI>; |
| pm_qos = <&qos_isp>, |
| <&qos_vicap0>, |
| <&qos_vicap1>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@RK3568_PD_VO { |
| reg = <RK3568_PD_VO>; |
| clocks = <&cru HCLK_VO>, |
| <&cru PCLK_VO>, |
| <&cru ACLK_VOP_PRE>; |
| pm_qos = <&qos_hdcp>, |
| <&qos_vop_m0>, |
| <&qos_vop_m1>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@RK3568_PD_RGA { |
| reg = <RK3568_PD_RGA>; |
| clocks = <&cru HCLK_RGA_PRE>, |
| <&cru PCLK_RGA_PRE>; |
| pm_qos = <&qos_ebc>, |
| <&qos_iep>, |
| <&qos_jpeg_dec>, |
| <&qos_jpeg_enc>, |
| <&qos_rga_rd>, |
| <&qos_rga_wr>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@RK3568_PD_VPU { |
| reg = <RK3568_PD_VPU>; |
| clocks = <&cru HCLK_VPU_PRE>; |
| pm_qos = <&qos_vpu>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@RK3568_PD_RKVDEC { |
| clocks = <&cru HCLK_RKVDEC_PRE>; |
| reg = <RK3568_PD_RKVDEC>; |
| pm_qos = <&qos_rkvdec>; |
| #power-domain-cells = <0>; |
| }; |
| |
| power-domain@RK3568_PD_RKVENC { |
| reg = <RK3568_PD_RKVENC>; |
| clocks = <&cru HCLK_RKVENC_PRE>; |
| pm_qos = <&qos_rkvenc_rd_m0>, |
| <&qos_rkvenc_rd_m1>, |
| <&qos_rkvenc_wr_m0>; |
| #power-domain-cells = <0>; |
| }; |
| }; |
| }; |
| |
| gpu: gpu@fde60000 { |
| compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; |
| reg = <0x0 0xfde60000 0x0 0x4000>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "job", "mmu", "gpu"; |
| clocks = <&scmi_clk 1>, <&cru CLK_GPU>; |
| clock-names = "gpu", "bus"; |
| #cooling-cells = <2>; |
| operating-points-v2 = <&gpu_opp_table>; |
| power-domains = <&power RK3568_PD_GPU>; |
| status = "disabled"; |
| }; |
| |
| vpu: video-codec@fdea0400 { |
| compatible = "rockchip,rk3568-vpu"; |
| reg = <0x0 0xfdea0000 0x0 0x800>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "vdpu"; |
| clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; |
| clock-names = "aclk", "hclk"; |
| iommus = <&vdpu_mmu>; |
| power-domains = <&power RK3568_PD_VPU>; |
| }; |
| |
| vdpu_mmu: iommu@fdea0800 { |
| compatible = "rockchip,rk3568-iommu"; |
| reg = <0x0 0xfdea0800 0x0 0x40>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "aclk", "iface"; |
| clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; |
| power-domains = <&power RK3568_PD_VPU>; |
| #iommu-cells = <0>; |
| }; |
| |
| rga: rga@fdeb0000 { |
| compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; |
| reg = <0x0 0xfdeb0000 0x0 0x180>; |
| interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; |
| clock-names = "aclk", "hclk", "sclk"; |
| resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; |
| reset-names = "core", "axi", "ahb"; |
| power-domains = <&power RK3568_PD_RGA>; |
| }; |
| |
| vepu: video-codec@fdee0000 { |
| compatible = "rockchip,rk3568-vepu"; |
| reg = <0x0 0xfdee0000 0x0 0x800>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; |
| clock-names = "aclk", "hclk"; |
| iommus = <&vepu_mmu>; |
| power-domains = <&power RK3568_PD_RGA>; |
| }; |
| |
| vepu_mmu: iommu@fdee0800 { |
| compatible = "rockchip,rk3568-iommu"; |
| reg = <0x0 0xfdee0800 0x0 0x40>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; |
| clock-names = "aclk", "iface"; |
| power-domains = <&power RK3568_PD_RGA>; |
| #iommu-cells = <0>; |
| }; |
| |
| sdmmc2: mmc@fe000000 { |
| compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| reg = <0x0 0xfe000000 0x0 0x4000>; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, |
| <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; |
| clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
| fifo-depth = <0x100>; |
| max-frequency = <150000000>; |
| resets = <&cru SRST_SDMMC2>; |
| reset-names = "reset"; |
| status = "disabled"; |
| }; |
| |
| gmac1: ethernet@fe010000 { |
| compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; |
| reg = <0x0 0xfe010000 0x0 0x10000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq", "eth_wake_irq"; |
| clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, |
| <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, |
| <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, |
| <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; |
| clock-names = "stmmaceth", "mac_clk_rx", |
| "mac_clk_tx", "clk_mac_refout", |
| "aclk_mac", "pclk_mac", |
| "clk_mac_speed", "ptp_ref"; |
| resets = <&cru SRST_A_GMAC1>; |
| reset-names = "stmmaceth"; |
| rockchip,grf = <&grf>; |
| snps,axi-config = <&gmac1_stmmac_axi_setup>; |
| snps,mixed-burst; |
| snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; |
| snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; |
| snps,tso; |
| status = "disabled"; |
| |
| mdio1: mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| }; |
| |
| gmac1_stmmac_axi_setup: stmmac-axi-config { |
| snps,blen = <0 0 0 0 16 8 4>; |
| snps,rd_osr_lmt = <8>; |
| snps,wr_osr_lmt = <4>; |
| }; |
| |
| gmac1_mtl_rx_setup: rx-queues-config { |
| snps,rx-queues-to-use = <1>; |
| queue0 {}; |
| }; |
| |
| gmac1_mtl_tx_setup: tx-queues-config { |
| snps,tx-queues-to-use = <1>; |
| queue0 {}; |
| }; |
| }; |
| |
| vop: vop@fe040000 { |
| reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; |
| reg-names = "vop", "gamma-lut"; |
| interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, |
| <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; |
| clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; |
| iommus = <&vop_mmu>; |
| power-domains = <&power RK3568_PD_VO>; |
| rockchip,grf = <&grf>; |
| status = "disabled"; |
| |
| vop_out: ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| vp0: port@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| vp1: port@1 { |
| reg = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| vp2: port@2 { |
| reg = <2>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| }; |
| |
| vop_mmu: iommu@fe043e00 { |
| compatible = "rockchip,rk3568-iommu"; |
| reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; |
| interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; |
| clock-names = "aclk", "iface"; |
| #iommu-cells = <0>; |
| power-domains = <&power RK3568_PD_VO>; |
| status = "disabled"; |
| }; |
| |
| dsi0: dsi@fe060000 { |
| compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; |
| reg = <0x00 0xfe060000 0x00 0x10000>; |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "pclk"; |
| clocks = <&cru PCLK_DSITX_0>; |
| phy-names = "dphy"; |
| phys = <&dsi_dphy0>; |
| power-domains = <&power RK3568_PD_VO>; |
| reset-names = "apb"; |
| resets = <&cru SRST_P_DSITX_0>; |
| rockchip,grf = <&grf>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| dsi0_in: port@0 { |
| reg = <0>; |
| }; |
| |
| dsi0_out: port@1 { |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| dsi1: dsi@fe070000 { |
| compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; |
| reg = <0x0 0xfe070000 0x0 0x10000>; |
| interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "pclk"; |
| clocks = <&cru PCLK_DSITX_1>; |
| phy-names = "dphy"; |
| phys = <&dsi_dphy1>; |
| power-domains = <&power RK3568_PD_VO>; |
| reset-names = "apb"; |
| resets = <&cru SRST_P_DSITX_1>; |
| rockchip,grf = <&grf>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| dsi1_in: port@0 { |
| reg = <0>; |
| }; |
| |
| dsi1_out: port@1 { |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| hdmi: hdmi@fe0a0000 { |
| compatible = "rockchip,rk3568-dw-hdmi"; |
| reg = <0x0 0xfe0a0000 0x0 0x20000>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru PCLK_HDMI_HOST>, |
| <&cru CLK_HDMI_SFR>, |
| <&cru CLK_HDMI_CEC>, |
| <&pmucru CLK_HDMI_REF>, |
| <&cru HCLK_VO>; |
| clock-names = "iahb", "isfr", "cec", "ref"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; |
| power-domains = <&power RK3568_PD_VO>; |
| reg-io-width = <4>; |
| rockchip,grf = <&grf>; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| hdmi_in: port@0 { |
| reg = <0>; |
| }; |
| |
| hdmi_out: port@1 { |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| qos_gpu: qos@fe128000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe128000 0x0 0x20>; |
| }; |
| |
| qos_rkvenc_rd_m0: qos@fe138080 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe138080 0x0 0x20>; |
| }; |
| |
| qos_rkvenc_rd_m1: qos@fe138100 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe138100 0x0 0x20>; |
| }; |
| |
| qos_rkvenc_wr_m0: qos@fe138180 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe138180 0x0 0x20>; |
| }; |
| |
| qos_isp: qos@fe148000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe148000 0x0 0x20>; |
| }; |
| |
| qos_vicap0: qos@fe148080 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe148080 0x0 0x20>; |
| }; |
| |
| qos_vicap1: qos@fe148100 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe148100 0x0 0x20>; |
| }; |
| |
| qos_vpu: qos@fe150000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe150000 0x0 0x20>; |
| }; |
| |
| qos_ebc: qos@fe158000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe158000 0x0 0x20>; |
| }; |
| |
| qos_iep: qos@fe158100 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe158100 0x0 0x20>; |
| }; |
| |
| qos_jpeg_dec: qos@fe158180 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe158180 0x0 0x20>; |
| }; |
| |
| qos_jpeg_enc: qos@fe158200 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe158200 0x0 0x20>; |
| }; |
| |
| qos_rga_rd: qos@fe158280 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe158280 0x0 0x20>; |
| }; |
| |
| qos_rga_wr: qos@fe158300 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe158300 0x0 0x20>; |
| }; |
| |
| qos_npu: qos@fe180000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe180000 0x0 0x20>; |
| }; |
| |
| qos_pcie2x1: qos@fe190000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe190000 0x0 0x20>; |
| }; |
| |
| qos_sata1: qos@fe190280 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe190280 0x0 0x20>; |
| }; |
| |
| qos_sata2: qos@fe190300 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe190300 0x0 0x20>; |
| }; |
| |
| qos_usb3_0: qos@fe190380 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe190380 0x0 0x20>; |
| }; |
| |
| qos_usb3_1: qos@fe190400 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe190400 0x0 0x20>; |
| }; |
| |
| qos_rkvdec: qos@fe198000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe198000 0x0 0x20>; |
| }; |
| |
| qos_hdcp: qos@fe1a8000 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe1a8000 0x0 0x20>; |
| }; |
| |
| qos_vop_m0: qos@fe1a8080 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe1a8080 0x0 0x20>; |
| }; |
| |
| qos_vop_m1: qos@fe1a8100 { |
| compatible = "rockchip,rk3568-qos", "syscon"; |
| reg = <0x0 0xfe1a8100 0x0 0x20>; |
| }; |
| |
| dfi: dfi@fe230000 { |
| compatible = "rockchip,rk3568-dfi"; |
| reg = <0x00 0xfe230000 0x00 0x400>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| rockchip,pmu = <&pmugrf>; |
| }; |
| |
| pcie2x1: pcie@fe260000 { |
| compatible = "rockchip,rk3568-pcie"; |
| reg = <0x3 0xc0000000 0x0 0x00400000>, |
| <0x0 0xfe260000 0x0 0x00010000>, |
| <0x0 0xf4000000 0x0 0x00100000>; |
| reg-names = "dbi", "apb", "config"; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "sys", "pmc", "msg", "legacy", "err"; |
| bus-range = <0x0 0xf>; |
| clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, |
| <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, |
| <&cru CLK_PCIE20_AUX_NDFT>; |
| clock-names = "aclk_mst", "aclk_slv", |
| "aclk_dbi", "pclk", "aux"; |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0 0 0 1 &pcie_intc 0>, |
| <0 0 0 2 &pcie_intc 1>, |
| <0 0 0 3 &pcie_intc 2>, |
| <0 0 0 4 &pcie_intc 3>; |
| linux,pci-domain = <0>; |
| num-ib-windows = <6>; |
| num-ob-windows = <2>; |
| max-link-speed = <2>; |
| msi-map = <0x0 &gic 0x0 0x1000>; |
| num-lanes = <1>; |
| phys = <&combphy2 PHY_TYPE_PCIE>; |
| phy-names = "pcie-phy"; |
| power-domains = <&power RK3568_PD_PIPE>; |
| ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, |
| <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, |
| <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; |
| resets = <&cru SRST_PCIE20_POWERUP>; |
| reset-names = "pipe"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| status = "disabled"; |
| |
| pcie_intc: legacy-interrupt-controller { |
| #address-cells = <0>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; |
| }; |
| }; |
| |
| sdmmc0: mmc@fe2b0000 { |
| compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| reg = <0x0 0xfe2b0000 0x0 0x4000>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, |
| <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; |
| clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
| fifo-depth = <0x100>; |
| max-frequency = <150000000>; |
| resets = <&cru SRST_SDMMC0>; |
| reset-names = "reset"; |
| status = "disabled"; |
| }; |
| |
| sdmmc1: mmc@fe2c0000 { |
| compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| reg = <0x0 0xfe2c0000 0x0 0x4000>; |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, |
| <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; |
| clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; |
| fifo-depth = <0x100>; |
| max-frequency = <150000000>; |
| resets = <&cru SRST_SDMMC1>; |
| reset-names = "reset"; |
| status = "disabled"; |
| }; |
| |
| sfc: spi@fe300000 { |
| compatible = "rockchip,sfc"; |
| reg = <0x0 0xfe300000 0x0 0x4000>; |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; |
| clock-names = "clk_sfc", "hclk_sfc"; |
| pinctrl-0 = <&fspi_pins>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| sdhci: mmc@fe310000 { |
| compatible = "rockchip,rk3568-dwcmshc"; |
| reg = <0x0 0xfe310000 0x0 0x10000>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; |
| assigned-clock-rates = <200000000>, <24000000>; |
| clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, |
| <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, |
| <&cru TCLK_EMMC>; |
| clock-names = "core", "bus", "axi", "block", "timer"; |
| status = "disabled"; |
| }; |
| |
| rng: rng@fe388000 { |
| compatible = "rockchip,rk3568-rng"; |
| reg = <0x0 0xfe388000 0x0 0x4000>; |
| clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; |
| clock-names = "core", "ahb"; |
| resets = <&cru SRST_TRNG_NS>; |
| status = "disabled"; |
| }; |
| |
| i2s0_8ch: i2s@fe400000 { |
| compatible = "rockchip,rk3568-i2s-tdm"; |
| reg = <0x0 0xfe400000 0x0 0x1000>; |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; |
| assigned-clock-rates = <1188000000>, <1188000000>; |
| clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; |
| clock-names = "mclk_tx", "mclk_rx", "hclk"; |
| dmas = <&dmac1 0>; |
| dma-names = "tx"; |
| resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; |
| reset-names = "tx-m", "rx-m"; |
| rockchip,grf = <&grf>; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2s1_8ch: i2s@fe410000 { |
| compatible = "rockchip,rk3568-i2s-tdm"; |
| reg = <0x0 0xfe410000 0x0 0x1000>; |
| interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; |
| assigned-clock-rates = <1188000000>, <1188000000>; |
| clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, |
| <&cru HCLK_I2S1_8CH>; |
| clock-names = "mclk_tx", "mclk_rx", "hclk"; |
| dmas = <&dmac1 3>, <&dmac1 2>; |
| dma-names = "rx", "tx"; |
| resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; |
| reset-names = "tx-m", "rx-m"; |
| rockchip,grf = <&grf>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx |
| &i2s1m0_lrcktx &i2s1m0_lrckrx |
| &i2s1m0_sdi0 &i2s1m0_sdi1 |
| &i2s1m0_sdi2 &i2s1m0_sdi3 |
| &i2s1m0_sdo0 &i2s1m0_sdo1 |
| &i2s1m0_sdo2 &i2s1m0_sdo3>; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2s2_2ch: i2s@fe420000 { |
| compatible = "rockchip,rk3568-i2s-tdm"; |
| reg = <0x0 0xfe420000 0x0 0x1000>; |
| interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
| assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; |
| assigned-clock-rates = <1188000000>; |
| clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; |
| clock-names = "mclk_tx", "mclk_rx", "hclk"; |
| dmas = <&dmac1 4>, <&dmac1 5>; |
| dma-names = "tx", "rx"; |
| resets = <&cru SRST_M_I2S2_2CH>; |
| reset-names = "tx-m"; |
| rockchip,grf = <&grf>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2s2m0_sclktx |
| &i2s2m0_lrcktx |
| &i2s2m0_sdi |
| &i2s2m0_sdo>; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2s3_2ch: i2s@fe430000 { |
| compatible = "rockchip,rk3568-i2s-tdm"; |
| reg = <0x0 0xfe430000 0x0 0x1000>; |
| interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, |
| <&cru HCLK_I2S3_2CH>; |
| clock-names = "mclk_tx", "mclk_rx", "hclk"; |
| dmas = <&dmac1 6>, <&dmac1 7>; |
| dma-names = "tx", "rx"; |
| resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; |
| reset-names = "tx-m", "rx-m"; |
| rockchip,grf = <&grf>; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pdm: pdm@fe440000 { |
| compatible = "rockchip,rk3568-pdm"; |
| reg = <0x0 0xfe440000 0x0 0x1000>; |
| interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; |
| clock-names = "pdm_clk", "pdm_hclk"; |
| dmas = <&dmac1 9>; |
| dma-names = "rx"; |
| pinctrl-0 = <&pdmm0_clk |
| &pdmm0_clk1 |
| &pdmm0_sdi0 |
| &pdmm0_sdi1 |
| &pdmm0_sdi2 |
| &pdmm0_sdi3>; |
| pinctrl-names = "default"; |
| resets = <&cru SRST_M_PDM>; |
| reset-names = "pdm-m"; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spdif: spdif@fe460000 { |
| compatible = "rockchip,rk3568-spdif"; |
| reg = <0x0 0xfe460000 0x0 0x1000>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "mclk", "hclk"; |
| clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; |
| dmas = <&dmac1 1>; |
| dma-names = "tx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spdifm0_tx>; |
| #sound-dai-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| dmac0: dma-controller@fe530000 { |
| compatible = "arm,pl330", "arm,primecell"; |
| reg = <0x0 0xfe530000 0x0 0x4000>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| arm,pl330-periph-burst; |
| clocks = <&cru ACLK_BUS>; |
| clock-names = "apb_pclk"; |
| #dma-cells = <1>; |
| }; |
| |
| dmac1: dma-controller@fe550000 { |
| compatible = "arm,pl330", "arm,primecell"; |
| reg = <0x0 0xfe550000 0x0 0x4000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| arm,pl330-periph-burst; |
| clocks = <&cru ACLK_BUS>; |
| clock-names = "apb_pclk"; |
| #dma-cells = <1>; |
| }; |
| |
| i2c1: i2c@fe5a0000 { |
| compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; |
| reg = <0x0 0xfe5a0000 0x0 0x1000>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; |
| clock-names = "i2c", "pclk"; |
| pinctrl-0 = <&i2c1_xfer>; |
| pinctrl-names = "default"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@fe5b0000 { |
| compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; |
| reg = <0x0 0xfe5b0000 0x0 0x1000>; |
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; |
| clock-names = "i2c", "pclk"; |
| pinctrl-0 = <&i2c2m0_xfer>; |
| pinctrl-names = "default"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@fe5c0000 { |
| compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; |
| reg = <0x0 0xfe5c0000 0x0 0x1000>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; |
| clock-names = "i2c", "pclk"; |
| pinctrl-0 = <&i2c3m0_xfer>; |
| pinctrl-names = "default"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@fe5d0000 { |
| compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; |
| reg = <0x0 0xfe5d0000 0x0 0x1000>; |
| interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; |
| clock-names = "i2c", "pclk"; |
| pinctrl-0 = <&i2c4m0_xfer>; |
| pinctrl-names = "default"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@fe5e0000 { |
| compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; |
| reg = <0x0 0xfe5e0000 0x0 0x1000>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; |
| clock-names = "i2c", "pclk"; |
| pinctrl-0 = <&i2c5m0_xfer>; |
| pinctrl-names = "default"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| wdt: watchdog@fe600000 { |
| compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; |
| reg = <0x0 0xfe600000 0x0 0x100>; |
| interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; |
| clock-names = "tclk", "pclk"; |
| }; |
| |
| spi0: spi@fe610000 { |
| compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; |
| reg = <0x0 0xfe610000 0x0 0x1000>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; |
| clock-names = "spiclk", "apb_pclk"; |
| dmas = <&dmac0 20>, <&dmac0 21>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@fe620000 { |
| compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; |
| reg = <0x0 0xfe620000 0x0 0x1000>; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; |
| clock-names = "spiclk", "apb_pclk"; |
| dmas = <&dmac0 22>, <&dmac0 23>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@fe630000 { |
| compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; |
| reg = <0x0 0xfe630000 0x0 0x1000>; |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; |
| clock-names = "spiclk", "apb_pclk"; |
| dmas = <&dmac0 24>, <&dmac0 25>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@fe640000 { |
| compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; |
| reg = <0x0 0xfe640000 0x0 0x1000>; |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; |
| clock-names = "spiclk", "apb_pclk"; |
| dmas = <&dmac0 26>, <&dmac0 27>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@fe650000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe650000 0x0 0x100>; |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 2>, <&dmac0 3>; |
| pinctrl-0 = <&uart1m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@fe660000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe660000 0x0 0x100>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 4>, <&dmac0 5>; |
| pinctrl-0 = <&uart2m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@fe670000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe670000 0x0 0x100>; |
| interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 6>, <&dmac0 7>; |
| pinctrl-0 = <&uart3m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@fe680000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe680000 0x0 0x100>; |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 8>, <&dmac0 9>; |
| pinctrl-0 = <&uart4m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@fe690000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe690000 0x0 0x100>; |
| interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 10>, <&dmac0 11>; |
| pinctrl-0 = <&uart5m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@fe6a0000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe6a0000 0x0 0x100>; |
| interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 12>, <&dmac0 13>; |
| pinctrl-0 = <&uart6m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@fe6b0000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe6b0000 0x0 0x100>; |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 14>, <&dmac0 15>; |
| pinctrl-0 = <&uart7m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@fe6c0000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe6c0000 0x0 0x100>; |
| interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 16>, <&dmac0 17>; |
| pinctrl-0 = <&uart8m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart9: serial@fe6d0000 { |
| compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; |
| reg = <0x0 0xfe6d0000 0x0 0x100>; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; |
| clock-names = "baudclk", "apb_pclk"; |
| dmas = <&dmac0 18>, <&dmac0 19>; |
| pinctrl-0 = <&uart9m0_xfer>; |
| pinctrl-names = "default"; |
| reg-io-width = <4>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| thermal_zones: thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <100>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsadc 0>; |
| |
| trips { |
| cpu_alert0: cpu_alert0 { |
| temperature = <70000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_alert1: cpu_alert1 { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_crit: cpu_crit { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu_alert0>; |
| cooling-device = |
| <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| gpu_thermal: gpu-thermal { |
| polling-delay-passive = <20>; /* milliseconds */ |
| polling-delay = <1000>; /* milliseconds */ |
| |
| thermal-sensors = <&tsadc 1>; |
| |
| trips { |
| gpu_threshold: gpu-threshold { |
| temperature = <70000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| gpu_target: gpu-target { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| gpu_crit: gpu-crit { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&gpu_target>; |
| cooling-device = |
| <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| tsadc: tsadc@fe710000 { |
| compatible = "rockchip,rk3568-tsadc"; |
| reg = <0x0 0xfe710000 0x0 0x100>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; |
| assigned-clock-rates = <17000000>, <700000>; |
| clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; |
| clock-names = "tsadc", "apb_pclk"; |
| resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, |
| <&cru SRST_TSADCPHY>; |
| rockchip,grf = <&grf>; |
| rockchip,hw-tshut-temp = <95000>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&tsadc_shutorg>; |
| pinctrl-1 = <&tsadc_pin>; |
| #thermal-sensor-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| saradc: saradc@fe720000 { |
| compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; |
| reg = <0x0 0xfe720000 0x0 0x100>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; |
| clock-names = "saradc", "apb_pclk"; |
| resets = <&cru SRST_P_SARADC>; |
| reset-names = "saradc-apb"; |
| #io-channel-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| pwm4: pwm@fe6e0000 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6e0000 0x0 0x10>; |
| clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm4_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm5: pwm@fe6e0010 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6e0010 0x0 0x10>; |
| clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm5_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm6: pwm@fe6e0020 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6e0020 0x0 0x10>; |
| clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm6_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm7: pwm@fe6e0030 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6e0030 0x0 0x10>; |
| clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm7_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm8: pwm@fe6f0000 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6f0000 0x0 0x10>; |
| clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm8m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm9: pwm@fe6f0010 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6f0010 0x0 0x10>; |
| clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm9m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm10: pwm@fe6f0020 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6f0020 0x0 0x10>; |
| clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm10m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm11: pwm@fe6f0030 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe6f0030 0x0 0x10>; |
| clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm11m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm12: pwm@fe700000 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe700000 0x0 0x10>; |
| clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm12m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm13: pwm@fe700010 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe700010 0x0 0x10>; |
| clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm13m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm14: pwm@fe700020 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe700020 0x0 0x10>; |
| clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm14m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm15: pwm@fe700030 { |
| compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; |
| reg = <0x0 0xfe700030 0x0 0x10>; |
| clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; |
| clock-names = "pwm", "pclk"; |
| pinctrl-0 = <&pwm15m0_pins>; |
| pinctrl-names = "default"; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| combphy1: phy@fe830000 { |
| compatible = "rockchip,rk3568-naneng-combphy"; |
| reg = <0x0 0xfe830000 0x0 0x100>; |
| clocks = <&pmucru CLK_PCIEPHY1_REF>, |
| <&cru PCLK_PIPEPHY1>, |
| <&cru PCLK_PIPE>; |
| clock-names = "ref", "apb", "pipe"; |
| assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; |
| assigned-clock-rates = <100000000>; |
| resets = <&cru SRST_PIPEPHY1>; |
| rockchip,pipe-grf = <&pipegrf>; |
| rockchip,pipe-phy-grf = <&pipe_phy_grf1>; |
| #phy-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| combphy2: phy@fe840000 { |
| compatible = "rockchip,rk3568-naneng-combphy"; |
| reg = <0x0 0xfe840000 0x0 0x100>; |
| clocks = <&pmucru CLK_PCIEPHY2_REF>, |
| <&cru PCLK_PIPEPHY2>, |
| <&cru PCLK_PIPE>; |
| clock-names = "ref", "apb", "pipe"; |
| assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; |
| assigned-clock-rates = <100000000>; |
| resets = <&cru SRST_PIPEPHY2>; |
| rockchip,pipe-grf = <&pipegrf>; |
| rockchip,pipe-phy-grf = <&pipe_phy_grf2>; |
| #phy-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| csi_dphy: phy@fe870000 { |
| compatible = "rockchip,rk3568-csi-dphy"; |
| reg = <0x0 0xfe870000 0x0 0x10000>; |
| clocks = <&cru PCLK_MIPICSIPHY>; |
| clock-names = "pclk"; |
| #phy-cells = <0>; |
| resets = <&cru SRST_P_MIPICSIPHY>; |
| reset-names = "apb"; |
| rockchip,grf = <&grf>; |
| status = "disabled"; |
| }; |
| |
| dsi_dphy0: mipi-dphy@fe850000 { |
| compatible = "rockchip,rk3568-dsi-dphy"; |
| reg = <0x0 0xfe850000 0x0 0x10000>; |
| clock-names = "ref", "pclk"; |
| clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; |
| #phy-cells = <0>; |
| power-domains = <&power RK3568_PD_VO>; |
| reset-names = "apb"; |
| resets = <&cru SRST_P_MIPIDSIPHY0>; |
| status = "disabled"; |
| }; |
| |
| dsi_dphy1: mipi-dphy@fe860000 { |
| compatible = "rockchip,rk3568-dsi-dphy"; |
| reg = <0x0 0xfe860000 0x0 0x10000>; |
| clock-names = "ref", "pclk"; |
| clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; |
| #phy-cells = <0>; |
| power-domains = <&power RK3568_PD_VO>; |
| reset-names = "apb"; |
| resets = <&cru SRST_P_MIPIDSIPHY1>; |
| status = "disabled"; |
| }; |
| |
| usb2phy0: usb2phy@fe8a0000 { |
| compatible = "rockchip,rk3568-usb2phy"; |
| reg = <0x0 0xfe8a0000 0x0 0x10000>; |
| clocks = <&pmucru CLK_USBPHY0_REF>; |
| clock-names = "phyclk"; |
| clock-output-names = "clk_usbphy0_480m"; |
| interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; |
| rockchip,usbgrf = <&usb2phy0_grf>; |
| #clock-cells = <0>; |
| status = "disabled"; |
| |
| usb2phy0_host: host-port { |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| usb2phy0_otg: otg-port { |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| usb2phy1: usb2phy@fe8b0000 { |
| compatible = "rockchip,rk3568-usb2phy"; |
| reg = <0x0 0xfe8b0000 0x0 0x10000>; |
| clocks = <&pmucru CLK_USBPHY1_REF>; |
| clock-names = "phyclk"; |
| clock-output-names = "clk_usbphy1_480m"; |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| rockchip,usbgrf = <&usb2phy1_grf>; |
| #clock-cells = <0>; |
| status = "disabled"; |
| |
| usb2phy1_host: host-port { |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| usb2phy1_otg: otg-port { |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| pinctrl: pinctrl { |
| compatible = "rockchip,rk3568-pinctrl"; |
| rockchip,grf = <&grf>; |
| rockchip,pmu = <&pmugrf>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio0: gpio@fdd60000 { |
| compatible = "rockchip,gpio-bank"; |
| reg = <0x0 0xfdd60000 0x0 0x100>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 0 32>; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio1: gpio@fe740000 { |
| compatible = "rockchip,gpio-bank"; |
| reg = <0x0 0xfe740000 0x0 0x100>; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 32 32>; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio2: gpio@fe750000 { |
| compatible = "rockchip,gpio-bank"; |
| reg = <0x0 0xfe750000 0x0 0x100>; |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 64 32>; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio3: gpio@fe760000 { |
| compatible = "rockchip,gpio-bank"; |
| reg = <0x0 0xfe760000 0x0 0x100>; |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 96 32>; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio4: gpio@fe770000 { |
| compatible = "rockchip,gpio-bank"; |
| reg = <0x0 0xfe770000 0x0 0x100>; |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; |
| gpio-controller; |
| gpio-ranges = <&pinctrl 0 128 32>; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| }; |
| |
| #include "rk3568-pinctrl.dtsi" |
