| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Unisoc SC9863A SoC DTS file |
| * |
| * Copyright (C) 2019, Unisoc Inc. |
| */ |
| |
| #include <dt-bindings/clock/sprd,sc9863a-clk.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include "sharkl3.dtsi" |
| |
| / { |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| core6 { |
| cpu = <&CPU6>; |
| }; |
| core7 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a55"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| cpu-idle-states = <&CORE_PD>; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| CORE_PD: core-pd { |
| compatible = "arm,idle-state"; |
| entry-latency-us = <4000>; |
| exit-latency-us = <4000>; |
| min-residency-us = <10000>; |
| local-timer-stop; |
| arm,psci-suspend-param = <0x00010000>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a55-pmu"; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| soc { |
| gic: interrupt-controller@14000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| redistributor-stride = <0x0 0x20000>; /* 128KB stride */ |
| #redistributor-regions = <1>; |
| interrupt-controller; |
| reg = <0x0 0x14000000 0 0x20000>, /* GICD */ |
| <0x0 0x14040000 0 0x100000>; /* GICR */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| ap_clk: clock-controller@21500000 { |
| compatible = "sprd,sc9863a-ap-clk"; |
| reg = <0 0x21500000 0 0x1000>; |
| clocks = <&ext_32k>, <&ext_26m>; |
| clock-names = "ext-32k", "ext-26m"; |
| #clock-cells = <1>; |
| }; |
| |
| aon_clk: clock-controller@402d0000 { |
| compatible = "sprd,sc9863a-aon-clk"; |
| reg = <0 0x402d0000 0 0x1000>; |
| clocks = <&ext_26m>, <&rco_100m>, |
| <&ext_32k>, <&ext_4m>; |
| clock-names = "ext-26m", "rco-100m", |
| "ext-32k", "ext-4m"; |
| #clock-cells = <1>; |
| }; |
| |
| mm_clk: clock-controller@60900000 { |
| compatible = "sprd,sc9863a-mm-clk"; |
| reg = <0 0x60900000 0 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| funnel@10001000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x10001000 0 0x1000>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel_soc_out_port: endpoint { |
| remote-endpoint = <&etb_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| funnel_soc_in_port: endpoint { |
| remote-endpoint = |
| <&funnel_ca55_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| etb@10003000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0 0x10003000 0 0x1000>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| in-ports { |
| port { |
| etb_in: endpoint { |
| remote-endpoint = |
| <&funnel_soc_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@12001000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x12001000 0 0x1000>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel_little_out_port: endpoint { |
| remote-endpoint = |
| <&etf_little_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_little_in_port0: endpoint { |
| remote-endpoint = <&etm0_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| funnel_little_in_port1: endpoint { |
| remote-endpoint = <&etm1_out>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| funnel_little_in_port2: endpoint { |
| remote-endpoint = <&etm2_out>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| funnel_little_in_port3: endpoint { |
| remote-endpoint = <&etm3_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etf@12002000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0 0x12002000 0 0x1000>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etf_little_out: endpoint { |
| remote-endpoint = |
| <&funnel_ca55_in_port0>; |
| }; |
| }; |
| }; |
| |
| in-port { |
| port { |
| etf_little_in: endpoint { |
| remote-endpoint = |
| <&funnel_little_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| etf@12003000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| reg = <0 0x12003000 0 0x1000>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etf_big_out: endpoint { |
| remote-endpoint = |
| <&funnel_ca55_in_port1>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| port { |
| etf_big_in: endpoint { |
| remote-endpoint = |
| <&funnel_big_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@12004000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x12004000 0 0x1000>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel_ca55_out_port: endpoint { |
| remote-endpoint = |
| <&funnel_soc_in_port>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_ca55_in_port0: endpoint { |
| remote-endpoint = |
| <&etf_little_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| funnel_ca55_in_port1: endpoint { |
| remote-endpoint = |
| <&etf_big_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel@12005000 { |
| compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
| reg = <0 0x12005000 0 0x1000>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel_big_out_port: endpoint { |
| remote-endpoint = |
| <&etf_big_in>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_big_in_port0: endpoint { |
| remote-endpoint = <&etm4_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| funnel_big_in_port1: endpoint { |
| remote-endpoint = <&etm5_out>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| funnel_big_in_port2: endpoint { |
| remote-endpoint = <&etm6_out>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| funnel_big_in_port3: endpoint { |
| remote-endpoint = <&etm7_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13040000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13040000 0 0x1000>; |
| cpu = <&CPU0>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm0_out: endpoint { |
| remote-endpoint = |
| <&funnel_little_in_port0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13140000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13140000 0 0x1000>; |
| cpu = <&CPU1>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm1_out: endpoint { |
| remote-endpoint = |
| <&funnel_little_in_port1>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13240000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13240000 0 0x1000>; |
| cpu = <&CPU2>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm2_out: endpoint { |
| remote-endpoint = |
| <&funnel_little_in_port2>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13340000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13340000 0 0x1000>; |
| cpu = <&CPU3>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm3_out: endpoint { |
| remote-endpoint = |
| <&funnel_little_in_port3>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13440000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13440000 0 0x1000>; |
| cpu = <&CPU4>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm4_out: endpoint { |
| remote-endpoint = |
| <&funnel_big_in_port0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13540000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13540000 0 0x1000>; |
| cpu = <&CPU5>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm5_out: endpoint { |
| remote-endpoint = |
| <&funnel_big_in_port1>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13640000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13640000 0 0x1000>; |
| cpu = <&CPU6>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm6_out: endpoint { |
| remote-endpoint = |
| <&funnel_big_in_port2>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm@13740000 { |
| compatible = "arm,coresight-etm4x", "arm,primecell"; |
| reg = <0 0x13740000 0 0x1000>; |
| cpu = <&CPU7>; |
| clocks = <&ext_26m>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| etm7_out: endpoint { |
| remote-endpoint = |
| <&funnel_big_in_port3>; |
| }; |
| }; |
| }; |
| }; |
| |
| ap-ahb { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| sdio0: mmc@20300000 { |
| compatible = "sprd,sdhci-r11"; |
| reg = <0 0x20300000 0 0x1000>; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&aon_clk CLK_SDIO0_2X>, |
| <&apahb_gate CLK_SDIO0_EB>; |
| clock-names = "sdio", "enable"; |
| assigned-clocks = <&aon_clk CLK_SDIO0_2X>; |
| assigned-clock-parents = <&rpll CLK_RPLL_390M>; |
| |
| bus-width = <4>; |
| no-sdio; |
| no-mmc; |
| }; |
| |
| sdio3: mmc@20600000 { |
| compatible = "sprd,sdhci-r11"; |
| reg = <0 0x20600000 0 0x1000>; |
| interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&aon_clk CLK_EMMC_2X>, |
| <&apahb_gate CLK_EMMC_EB>; |
| clock-names = "sdio", "enable"; |
| assigned-clocks = <&aon_clk CLK_EMMC_2X>; |
| assigned-clock-parents = <&rpll CLK_RPLL_390M>; |
| |
| bus-width = <8>; |
| non-removable; |
| no-sdio; |
| no-sd; |
| cap-mmc-hw-reset; |
| }; |
| }; |
| }; |
| }; |
