| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2021 Gateworks Corporation |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/input/linux-event-codes.h> |
| #include <dt-bindings/leds/common.h> |
| #include <dt-bindings/net/ti-dp83867.h> |
| #include <dt-bindings/phy/phy-imx8-pcie.h> |
| |
| #include "imx8mm.dtsi" |
| |
| / { |
| model = "Gateworks Venice GW7902 i.MX8MM board"; |
| compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; |
| |
| aliases { |
| ethernet1 = ð1; |
| usb0 = &usbotg1; |
| usb1 = &usbotg2; |
| }; |
| |
| chosen { |
| stdout-path = &uart2; |
| }; |
| |
| memory@40000000 { |
| device_type = "memory"; |
| reg = <0x0 0x40000000 0 0x80000000>; |
| }; |
| |
| can20m: can20m { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <20000000>; |
| clock-output-names = "can20m"; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| |
| key-user-pb { |
| label = "user_pb"; |
| gpios = <&gpio 2 GPIO_ACTIVE_LOW>; |
| linux,code = <BTN_0>; |
| }; |
| |
| key-user-pb1x { |
| label = "user_pb1x"; |
| linux,code = <BTN_1>; |
| interrupt-parent = <&gsc>; |
| interrupts = <0>; |
| }; |
| |
| key-erased { |
| label = "key_erased"; |
| linux,code = <BTN_2>; |
| interrupt-parent = <&gsc>; |
| interrupts = <1>; |
| }; |
| |
| key-eeprom-wp { |
| label = "eeprom_wp"; |
| linux,code = <BTN_3>; |
| interrupt-parent = <&gsc>; |
| interrupts = <2>; |
| }; |
| |
| key-tamper { |
| label = "tamper"; |
| linux,code = <BTN_4>; |
| interrupt-parent = <&gsc>; |
| interrupts = <5>; |
| }; |
| |
| switch-hold { |
| label = "switch_hold"; |
| linux,code = <BTN_5>; |
| interrupt-parent = <&gsc>; |
| interrupts = <7>; |
| }; |
| }; |
| |
| led-controller { |
| compatible = "gpio-leds"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpio_leds>; |
| |
| led-0 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "panel1"; |
| gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led-1 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "panel2"; |
| gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led-2 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "panel3"; |
| gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led-3 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "panel4"; |
| gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| |
| led-4 { |
| function = LED_FUNCTION_STATUS; |
| color = <LED_COLOR_ID_GREEN>; |
| label = "panel5"; |
| gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; |
| default-state = "off"; |
| }; |
| }; |
| |
| pcie0_refclk: pcie0-refclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| }; |
| |
| pps { |
| compatible = "pps-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pps>; |
| gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| }; |
| |
| reg_3p3v: regulator-3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "3P3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| reg_usb1_vbus: regulator-usb1 { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usb1>; |
| regulator-name = "usb_usb1_vbus"; |
| gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| }; |
| |
| reg_wifi: regulator-wifi { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_wl>; |
| regulator-name = "wifi"; |
| gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| startup-delay-us = <100>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <&buck2>; |
| }; |
| |
| &ddrc { |
| operating-points-v2 = <&ddrc_opp_table>; |
| |
| ddrc_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-25000000 { |
| opp-hz = /bits/ 64 <25000000>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| |
| opp-750000000 { |
| opp-hz = /bits/ 64 <750000000>; |
| }; |
| }; |
| }; |
| |
| &ecspi1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi1>; |
| cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| |
| can@0 { |
| compatible = "microchip,mcp2515"; |
| reg = <0>; |
| clocks = <&can20m>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| spi-max-frequency = <10000000>; |
| }; |
| }; |
| |
| /* off-board header */ |
| &ecspi2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi2>; |
| cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| local-mac-address = [00 00 00 00 00 00]; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| }; |
| }; |
| }; |
| |
| &gpio1 { |
| gpio-line-names = "", "", "", "", "", "", "", "", |
| "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &gpio2 { |
| gpio-line-names = "", "", "", "", "", "", "", "", |
| "uart2_en#", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &gpio3 { |
| gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &gpio4 { |
| gpio-line-names = "", "", "", "", "", "", "", "", |
| "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", |
| "lte_pwr#", "lte_rst", "lte_int", "", |
| "amp_gpio4", "app_gpio1", "vdd_4p0_en", "uart1_rs485", |
| "", "uart1_term", "uart1_half", "app_gpio2", |
| "mipi_gpio1", "", "", ""; |
| }; |
| |
| &gpio5 { |
| gpio-line-names = "", "", "", "mipi_gpio4", |
| "mipi_gpio3", "mipi_gpio2", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", "", |
| "", "", "", "", "", "", "", ""; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| gsc: gsc@20 { |
| compatible = "gw,gsc"; |
| reg = <0x20>; |
| pinctrl-0 = <&pinctrl_gsc>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <6 IRQ_TYPE_EDGE_FALLING>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| adc { |
| compatible = "gw,gsc-adc"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| channel@6 { |
| gw,mode = <0>; |
| reg = <0x06>; |
| label = "temp"; |
| }; |
| |
| channel@8 { |
| gw,mode = <3>; |
| reg = <0x08>; |
| label = "vdd_bat"; |
| }; |
| |
| channel@82 { |
| gw,mode = <2>; |
| reg = <0x82>; |
| label = "vin"; |
| gw,voltage-divider-ohms = <22100 1000>; |
| gw,voltage-offset-microvolt = <700000>; |
| }; |
| |
| channel@84 { |
| gw,mode = <2>; |
| reg = <0x84>; |
| label = "vin_4p0"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@86 { |
| gw,mode = <2>; |
| reg = <0x86>; |
| label = "vdd_3p3"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@88 { |
| gw,mode = <2>; |
| reg = <0x88>; |
| label = "vdd_0p9"; |
| }; |
| |
| channel@8c { |
| gw,mode = <2>; |
| reg = <0x8c>; |
| label = "vdd_soc"; |
| }; |
| |
| channel@8e { |
| gw,mode = <2>; |
| reg = <0x8e>; |
| label = "vdd_arm"; |
| }; |
| |
| channel@90 { |
| gw,mode = <2>; |
| reg = <0x90>; |
| label = "vdd_1p8"; |
| }; |
| |
| channel@92 { |
| gw,mode = <2>; |
| reg = <0x92>; |
| label = "vdd_dram"; |
| }; |
| |
| channel@98 { |
| gw,mode = <2>; |
| reg = <0x98>; |
| label = "vdd_1p0"; |
| }; |
| |
| channel@9a { |
| gw,mode = <2>; |
| reg = <0x9a>; |
| label = "vdd_2p5"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@9c { |
| gw,mode = <2>; |
| reg = <0x9c>; |
| label = "vdd_5p0"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| |
| channel@a2 { |
| gw,mode = <2>; |
| reg = <0xa2>; |
| label = "vdd_gsc"; |
| gw,voltage-divider-ohms = <10000 10000>; |
| }; |
| }; |
| }; |
| |
| gpio: gpio@23 { |
| compatible = "nxp,pca9555"; |
| reg = <0x23>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&gsc>; |
| interrupts = <4>; |
| }; |
| |
| pmic@4b { |
| compatible = "rohm,bd71847"; |
| reg = <0x4b>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pmic>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <8 IRQ_TYPE_LEVEL_LOW>; |
| rohm,reset-snvs-powered; |
| #clock-cells = <0>; |
| clocks = <&osc_32k>; |
| clock-output-names = "clk-32k-out"; |
| |
| regulators { |
| /* vdd_soc: 0.805-0.900V (typ=0.8V) */ |
| BUCK1 { |
| regulator-name = "buck1"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| }; |
| |
| /* vdd_arm: 0.805-1.0V (typ=0.9V) */ |
| buck2: BUCK2 { |
| regulator-name = "buck2"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| rohm,dvs-run-voltage = <1000000>; |
| rohm,dvs-idle-voltage = <900000>; |
| }; |
| |
| /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ |
| BUCK3 { |
| regulator-name = "buck3"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_3p3 */ |
| BUCK4 { |
| regulator-name = "buck4"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_1p8 */ |
| BUCK5 { |
| regulator-name = "buck5"; |
| regulator-min-microvolt = <1605000>; |
| regulator-max-microvolt = <1995000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_dram */ |
| BUCK6 { |
| regulator-name = "buck6"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* nvcc_snvs_1p8 */ |
| LDO1 { |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1600000>; |
| regulator-max-microvolt = <1900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdd_snvs_0p8 */ |
| LDO2 { |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| /* vdda_1p8 */ |
| LDO3 { |
| regulator-name = "ldo3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| LDO4 { |
| regulator-name = "ldo4"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| LDO6 { |
| regulator-name = "ldo6"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| eeprom@50 { |
| compatible = "atmel,24c02"; |
| reg = <0x50>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@51 { |
| compatible = "atmel,24c02"; |
| reg = <0x51>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@52 { |
| compatible = "atmel,24c02"; |
| reg = <0x52>; |
| pagesize = <16>; |
| }; |
| |
| eeprom@53 { |
| compatible = "atmel,24c02"; |
| reg = <0x53>; |
| pagesize = <16>; |
| }; |
| |
| rtc@68 { |
| compatible = "dallas,ds1672"; |
| reg = <0x68>; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| accelerometer@19 { |
| compatible = "st,lis2de12"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_accel>; |
| reg = <0x19>; |
| st,drdy-int-pin = <1>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <12 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| }; |
| |
| /* off-board header */ |
| &i2c3 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| pinctrl-1 = <&pinctrl_i2c3_gpio>; |
| scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| }; |
| |
| /* off-board header */ |
| &i2c4 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c4>; |
| pinctrl-1 = <&pinctrl_i2c4_gpio>; |
| scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| }; |
| |
| &pcie_phy { |
| fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; |
| fsl,clkreq-unsupported; |
| clocks = <&pcie0_refclk>; |
| clock-names = "ref"; |
| status = "okay"; |
| }; |
| |
| &pcie0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie0>; |
| reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; |
| clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&pcie0_refclk>, |
| <&clk IMX8MM_CLK_PCIE1_AUX>; |
| assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, |
| <&clk IMX8MM_CLK_PCIE1_CTRL>; |
| assigned-clock-rates = <10000000>, <250000000>; |
| assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, |
| <&clk IMX8MM_SYS_PLL2_250M>; |
| status = "okay"; |
| |
| pcie@0,0 { |
| reg = <0x0000 0 0 0 0>; |
| device_type = "pci"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| eth1: ethernet@0,0 { |
| reg = <0x0000 0 0 0 0>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| local-mac-address = [00 00 00 00 00 00]; |
| }; |
| }; |
| }; |
| |
| /* off-board header */ |
| &sai3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai3>; |
| assigned-clocks = <&clk IMX8MM_CLK_SAI3>; |
| assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <24576000>; |
| status = "okay"; |
| }; |
| |
| /* RS232/RS485/RS422 selectable */ |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; |
| rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; |
| cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| /* RS232 console */ |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| /* bluetooth HCI */ |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; |
| rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; |
| cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| |
| bluetooth { |
| compatible = "brcm,bcm4330-bt"; |
| shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart4>; |
| rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; |
| cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; |
| dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; |
| dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; |
| dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| dr_mode = "host"; |
| vbus-supply = <®_usb1_vbus>; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| dr_mode = "host"; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| /* SDIO WiFi */ |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>; |
| bus-width = <4>; |
| non-removable; |
| vmmc-supply = <®_wifi>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| |
| wifi@0 { |
| compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; |
| reg = <0>; |
| }; |
| }; |
| |
| /* eMMC */ |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ |
| MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */ |
| MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ |
| MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ |
| MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ |
| MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000041 /* LTE_INT */ |
| MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000041 /* LTE_RST# */ |
| MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000041 /* LTE_PWR */ |
| MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ |
| MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ |
| MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ |
| MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ |
| MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ |
| MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */ |
| MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ |
| MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ |
| MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ |
| MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ |
| MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ |
| MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ |
| >; |
| }; |
| |
| pinctrl_accel: accelgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 |
| MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ |
| MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ |
| >; |
| }; |
| |
| pinctrl_gsc: gscgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2_gpio: i2c2gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c3_gpio: i2c3gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 |
| MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c4: i2c4grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c4_gpio: i2c4gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3 |
| MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_gpio_leds: gpioledgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 |
| MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 |
| MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 |
| MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 |
| MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 |
| >; |
| }; |
| |
| pinctrl_pcie0: pciegrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 |
| >; |
| }; |
| |
| pinctrl_pmic: pmicgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 |
| >; |
| }; |
| |
| pinctrl_pps: ppsgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ |
| >; |
| }; |
| |
| pinctrl_reg_wl: regwlgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ |
| >; |
| }; |
| |
| pinctrl_reg_usb1: regusb1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 |
| >; |
| }; |
| |
| pinctrl_sai3: sai3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 |
| MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 |
| MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 |
| MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 |
| MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 |
| >; |
| }; |
| |
| pinctrl_spi1: spi1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 |
| MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 |
| MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 |
| MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 |
| MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ |
| >; |
| }; |
| |
| pinctrl_spi2: spi2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 |
| MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 |
| MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 |
| MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 |
| MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ |
| MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ |
| >; |
| }; |
| |
| pinctrl_uart1_gpio: uart1gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ |
| MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ |
| MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 |
| >; |
| }; |
| |
| pinctrl_uart3_gpio: uart3_gpiogrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 |
| MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ |
| MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ |
| >; |
| }; |
| |
| pinctrl_uart4: uart4grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 |
| MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ |
| MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ |
| MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ |
| MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ |
| MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ |
| MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ |
| MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ |
| MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 |
| MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 |
| MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 |
| MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 |
| MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 |
| MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 |
| MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 |
| MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |
