arch/mips/boot/dts/lantiq/danube.dtsi

// SPDX-License-Identifier: GPL-2.0
/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "lantiq,xway", "lantiq,danube";

	cpus {
		cpu@0 {
			compatible = "mips,mips24Kc";
		};
	};

	biu@1f800000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "lantiq,biu", "simple-bus";
		reg = <0x1f800000 0x800000>;
		ranges = <0x0 0x1f800000 0x7fffff>;

		icu0: icu@80200 {
			#interrupt-cells = <1>;
			interrupt-controller;
			compatible = "lantiq,icu";
			reg = <0x80200 0x120>;
		};

		watchdog@803f0 {
			compatible = "lantiq,wdt";
			reg = <0x803f0 0x10>;
		};
	};

	sram@1f000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "lantiq,sram";
		reg = <0x1f000000 0x800000>;
		ranges = <0x0 0x1f000000 0x7fffff>;

		eiu0: eiu@101000 {
			#interrupt-cells = <1>;
			interrupt-controller;
			interrupt-parent;
			compatible = "lantiq,eiu-xway";
			reg = <0x101000 0x1000>;
		};

		pmu0: pmu@102000 {
			compatible = "lantiq,pmu-xway";
			reg = <0x102000 0x1000>;
		};

		cgu0: cgu@103000 {
			compatible = "lantiq,cgu-xway";
			reg = <0x103000 0x1000>;
			#clock-cells = <1>;
		};

		rcu0: rcu@203000 {
			compatible = "lantiq,rcu-xway";
			reg = <0x203000 0x1000>;
		};
	};

	fpi@10000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "lantiq,fpi", "simple-bus";
		ranges = <0x0 0x10000000 0xeefffff>;
		reg = <0x10000000 0xef00000>;

		gptu@e100a00 {
			compatible = "lantiq,gptu-xway";
			reg = <0xe100a00 0x100>;
		};

		serial@e100c00 {
			compatible = "lantiq,asc";
			reg = <0xe100c00 0x400>;
			interrupt-parent = <&icu0>;
			interrupts = <112 113 114>;
		};

		dma0: dma@e104100 {
			compatible = "lantiq,dma-xway";
			reg = <0xe104100 0x800>;
		};

		ebu0: ebu@e105300 {
			compatible = "lantiq,ebu-xway";
			reg = <0xe105300 0x100>;
		};

		pci0: pci@e105400 {
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			compatible = "lantiq,pci-xway";
			bus-range = <0x0 0x0>;
			ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000	/* pci memory */
				  0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
			reg = <0x7000000 0x8000		/* config space */
				0xe105400 0x400>;	/* pci bridge */
		};
	};
};