Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: DesignWare based PCIe Root Complex controller on Rockchip SoCs

maintainers:
  - Shawn Lin <shawn.lin@rock-chips.com>
  - Simon Xue <xxm@rock-chips.com>
  - Heiko Stuebner <heiko@sntech.de>

description: |+
  RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
  PCIe IP and thus inherits all the common properties defined in
  snps,dw-pcie.yaml.

allOf:
  - $ref: /schemas/pci/snps,dw-pcie.yaml#
  - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml#

properties:
  compatible:
    oneOf:
      - const: rockchip,rk3568-pcie
      - items:
          - enum:
              - rockchip,rk3588-pcie
          - const: rockchip,rk3568-pcie

  reg:
    items:
      - description: Data Bus Interface (DBI) registers
      - description: Rockchip designed configuration registers
      - description: Config registers

  reg-names:
    items:
      - const: dbi
      - const: apb
      - const: config

  legacy-interrupt-controller:
    description: Interrupt controller node for handling legacy PCI interrupts.
    type: object
    additionalProperties: false
    properties:
      "#address-cells":
        const: 0

      "#interrupt-cells":
        const: 1

      interrupt-controller: true

      interrupts:
        items:
          - description: combined legacy interrupt
    required:
      - "#address-cells"
      - "#interrupt-cells"
      - interrupt-controller
      - interrupts

  msi-map: true

  ranges:
    minItems: 2
    maxItems: 3

  vpcie3v3-supply: true

required:
  - msi-map

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        pcie3x2: pcie@fe280000 {
            compatible = "rockchip,rk3568-pcie";
            reg = <0x3 0xc0800000 0x0 0x390000>,
                  <0x0 0xfe280000 0x0 0x10000>,
                  <0x3 0x80000000 0x0 0x100000>;
            reg-names = "dbi", "apb", "config";
            bus-range = <0x20 0x2f>;
            clocks = <&cru 143>, <&cru 144>,
                     <&cru 145>, <&cru 146>,
                     <&cru 147>;
            clock-names = "aclk_mst", "aclk_slv",
                          "aclk_dbi", "pclk",
                          "aux";
            device_type = "pci";
            interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "sys", "pmc", "msg", "legacy", "err";
            linux,pci-domain = <2>;
            max-link-speed = <2>;
            msi-map = <0x2000 &its 0x2000 0x1000>;
            num-lanes = <2>;
            phys = <&pcie30phy>;
            phy-names = "pcie-phy";
            power-domains = <&power 15>;
            ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
                     <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
            resets = <&cru 193>;
            reset-names = "pipe";
            #address-cells = <3>;
            #size-cells = <2>;

            legacy-interrupt-controller {
                interrupt-controller;
                #address-cells = <0>;
                #interrupt-cells = <1>;
                interrupt-parent = <&gic>;
                interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
            };
        };
    };
...