| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. |
| */ |
| |
| #include <linux/clk-provider.h> |
| #include <linux/module.h> |
| #include <linux/mod_devicetable.h> |
| #include <linux/of.h> |
| #include <linux/platform_device.h> |
| #include <linux/regmap.h> |
| |
| #include <dt-bindings/clock/qcom,sm4450-gpucc.h> |
| |
| #include "clk-alpha-pll.h" |
| #include "clk-branch.h" |
| #include "clk-pll.h" |
| #include "clk-rcg.h" |
| #include "clk-regmap.h" |
| #include "clk-regmap-divider.h" |
| #include "common.h" |
| #include "gdsc.h" |
| #include "reset.h" |
| |
| enum { |
| DT_BI_TCXO, |
| DT_GPLL0_OUT_MAIN, |
| DT_GPLL0_OUT_MAIN_DIV, |
| }; |
| |
| enum { |
| P_BI_TCXO, |
| P_GPLL0_OUT_MAIN, |
| P_GPLL0_OUT_MAIN_DIV, |
| P_GPU_CC_PLL0_OUT_EVEN, |
| P_GPU_CC_PLL0_OUT_MAIN, |
| P_GPU_CC_PLL0_OUT_ODD, |
| P_GPU_CC_PLL1_OUT_EVEN, |
| P_GPU_CC_PLL1_OUT_MAIN, |
| P_GPU_CC_PLL1_OUT_ODD, |
| }; |
| |
| static const struct pll_vco lucid_evo_vco[] = { |
| { 249600000, 2020000000, 0 }, |
| }; |
| |
| /* 680.0 MHz Configuration */ |
| static const struct alpha_pll_config gpu_cc_pll0_config = { |
| .l = 0x23, |
| .alpha = 0x6aaa, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00182261, |
| .config_ctl_hi1_val = 0x32aa299c, |
| .user_ctl_val = 0x00000000, |
| .user_ctl_hi_val = 0x00000805, |
| }; |
| |
| static struct clk_alpha_pll gpu_cc_pll0 = { |
| .offset = 0x0, |
| .vco_table = lucid_evo_vco, |
| .num_vco = ARRAY_SIZE(lucid_evo_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], |
| .clkr = { |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_pll0", |
| .parent_data = &(const struct clk_parent_data) { |
| .index = DT_BI_TCXO, |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_evo_ops, |
| }, |
| }, |
| }; |
| |
| /* 500.0 MHz Configuration */ |
| static const struct alpha_pll_config gpu_cc_pll1_config = { |
| .l = 0x1a, |
| .alpha = 0xaaa, |
| .config_ctl_val = 0x20485699, |
| .config_ctl_hi_val = 0x00182261, |
| .config_ctl_hi1_val = 0x32aa299c, |
| .user_ctl_val = 0x00000000, |
| .user_ctl_hi_val = 0x00000805, |
| }; |
| |
| static struct clk_alpha_pll gpu_cc_pll1 = { |
| .offset = 0x1000, |
| .vco_table = lucid_evo_vco, |
| .num_vco = ARRAY_SIZE(lucid_evo_vco), |
| .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], |
| .clkr = { |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_pll1", |
| .parent_data = &(const struct clk_parent_data) { |
| .index = DT_BI_TCXO, |
| }, |
| .num_parents = 1, |
| .ops = &clk_alpha_pll_lucid_evo_ops, |
| }, |
| }, |
| }; |
| |
| static const struct parent_map gpu_cc_parent_map_0[] = { |
| { P_BI_TCXO, 0 }, |
| { P_GPLL0_OUT_MAIN, 5 }, |
| { P_GPLL0_OUT_MAIN_DIV, 6 }, |
| }; |
| |
| static const struct clk_parent_data gpu_cc_parent_data_0[] = { |
| { .index = DT_BI_TCXO }, |
| { .index = DT_GPLL0_OUT_MAIN }, |
| { .index = DT_GPLL0_OUT_MAIN_DIV }, |
| }; |
| |
| static const struct parent_map gpu_cc_parent_map_1[] = { |
| { P_BI_TCXO, 0 }, |
| { P_GPU_CC_PLL0_OUT_MAIN, 1 }, |
| { P_GPU_CC_PLL1_OUT_MAIN, 3 }, |
| { P_GPLL0_OUT_MAIN, 5 }, |
| { P_GPLL0_OUT_MAIN_DIV, 6 }, |
| }; |
| |
| static const struct clk_parent_data gpu_cc_parent_data_1[] = { |
| { .index = DT_BI_TCXO }, |
| { .hw = &gpu_cc_pll0.clkr.hw }, |
| { .hw = &gpu_cc_pll1.clkr.hw }, |
| { .index = DT_GPLL0_OUT_MAIN }, |
| { .index = DT_GPLL0_OUT_MAIN_DIV }, |
| }; |
| |
| static const struct parent_map gpu_cc_parent_map_2[] = { |
| { P_BI_TCXO, 0 }, |
| { P_GPU_CC_PLL0_OUT_EVEN, 1 }, |
| { P_GPU_CC_PLL0_OUT_ODD, 2 }, |
| { P_GPU_CC_PLL1_OUT_EVEN, 3 }, |
| { P_GPU_CC_PLL1_OUT_ODD, 4 }, |
| { P_GPLL0_OUT_MAIN, 5 }, |
| }; |
| |
| static const struct clk_parent_data gpu_cc_parent_data_2[] = { |
| { .index = DT_BI_TCXO }, |
| { .hw = &gpu_cc_pll0.clkr.hw }, |
| { .hw = &gpu_cc_pll0.clkr.hw }, |
| { .hw = &gpu_cc_pll1.clkr.hw }, |
| { .hw = &gpu_cc_pll1.clkr.hw }, |
| { .index = DT_GPLL0_OUT_MAIN }, |
| }; |
| |
| static const struct parent_map gpu_cc_parent_map_3[] = { |
| { P_BI_TCXO, 0 }, |
| { P_GPU_CC_PLL1_OUT_MAIN, 3 }, |
| { P_GPLL0_OUT_MAIN, 5 }, |
| { P_GPLL0_OUT_MAIN_DIV, 6 }, |
| }; |
| |
| static const struct clk_parent_data gpu_cc_parent_data_3[] = { |
| { .index = DT_BI_TCXO }, |
| { .hw = &gpu_cc_pll1.clkr.hw }, |
| { .index = DT_GPLL0_OUT_MAIN }, |
| { .index = DT_GPLL0_OUT_MAIN_DIV }, |
| }; |
| |
| static const struct parent_map gpu_cc_parent_map_4[] = { |
| { P_BI_TCXO, 0 }, |
| }; |
| |
| static const struct clk_parent_data gpu_cc_parent_data_4[] = { |
| { .index = DT_BI_TCXO }, |
| }; |
| |
| static const struct freq_tbl ftbl_gpu_cc_ff_clk_src[] = { |
| F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 gpu_cc_ff_clk_src = { |
| .cmd_rcgr = 0x9474, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = gpu_cc_parent_map_0, |
| .freq_tbl = ftbl_gpu_cc_ff_clk_src, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_ff_clk_src", |
| .parent_data = gpu_cc_parent_data_0, |
| .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_rcg2 gpu_cc_gmu_clk_src = { |
| .cmd_rcgr = 0x9318, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = gpu_cc_parent_map_1, |
| .freq_tbl = ftbl_gpu_cc_ff_clk_src, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gmu_clk_src", |
| .parent_data = gpu_cc_parent_data_1, |
| .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = { |
| F(340000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(500000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(605000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(765000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(850000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(955000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| F(1010000000, P_GPU_CC_PLL0_OUT_EVEN, 2, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = { |
| .cmd_rcgr = 0x9070, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = gpu_cc_parent_map_2, |
| .freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gx_gfx3d_clk_src", |
| .parent_data = gpu_cc_parent_data_2, |
| .num_parents = ARRAY_SIZE(gpu_cc_parent_data_2), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { |
| F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 gpu_cc_hub_clk_src = { |
| .cmd_rcgr = 0x93ec, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = gpu_cc_parent_map_3, |
| .freq_tbl = ftbl_gpu_cc_hub_clk_src, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_hub_clk_src", |
| .parent_data = gpu_cc_parent_data_3, |
| .num_parents = ARRAY_SIZE(gpu_cc_parent_data_3), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static const struct freq_tbl ftbl_gpu_cc_xo_clk_src[] = { |
| F(19200000, P_BI_TCXO, 1, 0, 0), |
| { } |
| }; |
| |
| static struct clk_rcg2 gpu_cc_xo_clk_src = { |
| .cmd_rcgr = 0x9010, |
| .mnd_width = 0, |
| .hid_width = 5, |
| .parent_map = gpu_cc_parent_map_4, |
| .freq_tbl = ftbl_gpu_cc_xo_clk_src, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_xo_clk_src", |
| .parent_data = gpu_cc_parent_data_4, |
| .num_parents = ARRAY_SIZE(gpu_cc_parent_data_4), |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_rcg2_shared_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div gpu_cc_demet_div_clk_src = { |
| .reg = 0x9054, |
| .shift = 0, |
| .width = 4, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_demet_div_clk_src", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_xo_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_regmap_div_ro_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { |
| .reg = 0x9430, |
| .shift = 0, |
| .width = 4, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_hub_ahb_div_clk_src", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_hub_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_regmap_div_ro_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { |
| .reg = 0x942c, |
| .shift = 0, |
| .width = 4, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_hub_cx_int_div_clk_src", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_hub_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_regmap_div_ro_ops, |
| }, |
| }; |
| |
| static struct clk_regmap_div gpu_cc_xo_div_clk_src = { |
| .reg = 0x9050, |
| .shift = 0, |
| .width = 4, |
| .clkr.hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_xo_div_clk_src", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_xo_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_regmap_div_ro_ops, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_ahb_clk = { |
| .halt_reg = 0x911c, |
| .halt_check = BRANCH_HALT_DELAY, |
| .clkr = { |
| .enable_reg = 0x911c, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_ahb_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_hub_ahb_div_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_crc_ahb_clk = { |
| .halt_reg = 0x9120, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9120, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_crc_ahb_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_hub_ahb_div_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_cx_ff_clk = { |
| .halt_reg = 0x914c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x914c, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_cx_ff_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_ff_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_cx_gfx3d_clk = { |
| .halt_reg = 0x919c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x919c, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_cx_gfx3d_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_gx_gfx3d_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = { |
| .halt_reg = 0x91a0, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x91a0, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_cx_gfx3d_slv_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_gx_gfx3d_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_cx_gmu_clk = { |
| .halt_reg = 0x913c, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x913c, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_cx_gmu_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_gmu_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_aon_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { |
| .halt_reg = 0x9130, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9130, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_cx_snoc_dvm_clk", |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_cxo_clk = { |
| .halt_reg = 0x9144, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9144, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_cxo_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_xo_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_freq_measure_clk = { |
| .halt_reg = 0x9008, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9008, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_freq_measure_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_xo_div_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_gx_cxo_clk = { |
| .halt_reg = 0x90b8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x90b8, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gx_cxo_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_xo_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_gx_ff_clk = { |
| .halt_reg = 0x90c0, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x90c0, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gx_ff_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_ff_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_gx_gfx3d_clk = { |
| .halt_reg = 0x90a8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x90a8, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gx_gfx3d_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_gx_gfx3d_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_gx_gfx3d_rdvm_clk = { |
| .halt_reg = 0x90c8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x90c8, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gx_gfx3d_rdvm_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_gx_gfx3d_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_gx_gmu_clk = { |
| .halt_reg = 0x90bc, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x90bc, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gx_gmu_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_gmu_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_gx_vsense_clk = { |
| .halt_reg = 0x90b0, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x90b0, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_gx_vsense_clk", |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_hub_aon_clk = { |
| .halt_reg = 0x93e8, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x93e8, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_hub_aon_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_hub_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_aon_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_hub_cx_int_clk = { |
| .halt_reg = 0x9148, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9148, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_hub_cx_int_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_aon_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_memnoc_gfx_clk = { |
| .halt_reg = 0x9150, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9150, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_memnoc_gfx_clk", |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { |
| .halt_reg = 0x9288, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9288, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_mnd1x_0_gfx3d_clk", |
| .parent_hws = (const struct clk_hw*[]) { |
| &gpu_cc_gx_gfx3d_clk_src.clkr.hw, |
| }, |
| .num_parents = 1, |
| .flags = CLK_SET_RATE_PARENT, |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct clk_branch gpu_cc_sleep_clk = { |
| .halt_reg = 0x9134, |
| .halt_check = BRANCH_HALT, |
| .clkr = { |
| .enable_reg = 0x9134, |
| .enable_mask = BIT(0), |
| .hw.init = &(const struct clk_init_data) { |
| .name = "gpu_cc_sleep_clk", |
| .ops = &clk_branch2_ops, |
| }, |
| }, |
| }; |
| |
| static struct gdsc gpu_cc_cx_gdsc = { |
| .gdscr = 0x9108, |
| .gds_hw_ctrl = 0x953c, |
| .clk_dis_wait_val = 8, |
| .pd = { |
| .name = "gpu_cx_gdsc", |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = VOTABLE | RETAIN_FF_ENABLE, |
| }; |
| |
| static struct gdsc gpu_cc_gx_gdsc = { |
| .gdscr = 0x905c, |
| .clamp_io_ctrl = 0x9504, |
| .resets = (unsigned int []){ GPU_CC_GX_BCR, |
| GPU_CC_ACD_BCR, |
| GPU_CC_GX_ACD_IROOT_BCR }, |
| .reset_count = 3, |
| .pd = { |
| .name = "gpu_gx_gdsc", |
| .power_on = gdsc_gx_do_nothing_enable, |
| }, |
| .pwrsts = PWRSTS_OFF_ON, |
| .flags = CLAMP_IO | AON_RESET | SW_RESET | POLL_CFG_GDSCR, |
| }; |
| |
| static struct clk_regmap *gpu_cc_sm4450_clocks[] = { |
| [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, |
| [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, |
| [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr, |
| [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, |
| [GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr, |
| [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, |
| [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, |
| [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, |
| [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr, |
| [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr, |
| [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, |
| [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, |
| [GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr, |
| [GPU_CC_GX_FF_CLK] = &gpu_cc_gx_ff_clk.clkr, |
| [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, |
| [GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr, |
| [GPU_CC_GX_GFX3D_RDVM_CLK] = &gpu_cc_gx_gfx3d_rdvm_clk.clkr, |
| [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, |
| [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, |
| [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, |
| [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, |
| [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, |
| [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, |
| [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, |
| [GPU_CC_MEMNOC_GFX_CLK] = &gpu_cc_memnoc_gfx_clk.clkr, |
| [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, |
| [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, |
| [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, |
| [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, |
| [GPU_CC_XO_CLK_SRC] = &gpu_cc_xo_clk_src.clkr, |
| [GPU_CC_XO_DIV_CLK_SRC] = &gpu_cc_xo_div_clk_src.clkr, |
| }; |
| |
| static struct gdsc *gpu_cc_sm4450_gdscs[] = { |
| [GPU_CC_CX_GDSC] = &gpu_cc_cx_gdsc, |
| [GPU_CC_GX_GDSC] = &gpu_cc_gx_gdsc, |
| }; |
| |
| static const struct qcom_reset_map gpu_cc_sm4450_resets[] = { |
| [GPU_CC_CB_BCR] = { 0x93a0 }, |
| [GPU_CC_CX_BCR] = { 0x9104 }, |
| [GPU_CC_GX_BCR] = { 0x9058 }, |
| [GPU_CC_FAST_HUB_BCR] = { 0x93e4 }, |
| [GPU_CC_ACD_BCR] = { 0x9358 }, |
| [GPU_CC_FF_BCR] = { 0x9470 }, |
| [GPU_CC_GFX3D_AON_BCR] = { 0x9198 }, |
| [GPU_CC_GMU_BCR] = { 0x9314 }, |
| [GPU_CC_RBCPR_BCR] = { 0x91e0 }, |
| [GPU_CC_XO_BCR] = { 0x9000 }, |
| [GPU_CC_GX_ACD_IROOT_BCR] = { 0x958c }, |
| }; |
| |
| static const struct regmap_config gpu_cc_sm4450_regmap_config = { |
| .reg_bits = 32, |
| .reg_stride = 4, |
| .val_bits = 32, |
| .max_register = 0x95c0, |
| .fast_io = true, |
| }; |
| |
| static const struct qcom_cc_desc gpu_cc_sm4450_desc = { |
| .config = &gpu_cc_sm4450_regmap_config, |
| .clks = gpu_cc_sm4450_clocks, |
| .num_clks = ARRAY_SIZE(gpu_cc_sm4450_clocks), |
| .resets = gpu_cc_sm4450_resets, |
| .num_resets = ARRAY_SIZE(gpu_cc_sm4450_resets), |
| .gdscs = gpu_cc_sm4450_gdscs, |
| .num_gdscs = ARRAY_SIZE(gpu_cc_sm4450_gdscs), |
| }; |
| |
| static const struct of_device_id gpu_cc_sm4450_match_table[] = { |
| { .compatible = "qcom,sm4450-gpucc" }, |
| { } |
| }; |
| MODULE_DEVICE_TABLE(of, gpu_cc_sm4450_match_table); |
| |
| static int gpu_cc_sm4450_probe(struct platform_device *pdev) |
| { |
| struct regmap *regmap; |
| |
| regmap = qcom_cc_map(pdev, &gpu_cc_sm4450_desc); |
| if (IS_ERR(regmap)) |
| return PTR_ERR(regmap); |
| |
| clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); |
| clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); |
| |
| /* Keep some clocks always enabled */ |
| qcom_branch_set_clk_en(regmap, 0x93a4); /* GPU_CC_CB_CLK */ |
| qcom_branch_set_clk_en(regmap, 0x9004); /* GPU_CC_CXO_AON_CLK */ |
| qcom_branch_set_clk_en(regmap, 0x900c); /* GPU_CC_DEMET_CLK */ |
| |
| return qcom_cc_really_probe(&pdev->dev, &gpu_cc_sm4450_desc, regmap); |
| } |
| |
| static struct platform_driver gpu_cc_sm4450_driver = { |
| .probe = gpu_cc_sm4450_probe, |
| .driver = { |
| .name = "gpucc-sm4450", |
| .of_match_table = gpu_cc_sm4450_match_table, |
| }, |
| }; |
| |
| module_platform_driver(gpu_cc_sm4450_driver); |
| |
| MODULE_DESCRIPTION("QTI GPUCC SM4450 Driver"); |
| MODULE_LICENSE("GPL"); |
