| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* Copyright(c) 2009-2012 Realtek Corporation.*/ |
| |
| #ifndef __RTL92DE_TRX_H__ |
| #define __RTL92DE_TRX_H__ |
| |
| #define TX_DESC_SIZE 64 |
| #define TX_DESC_AGGR_SUBFRAME_SIZE 32 |
| |
| #define RX_DESC_SIZE 32 |
| |
| #define TX_DESC_NEXT_DESC_OFFSET 40 |
| #define USB_HWDESC_HEADER_LEN 32 |
| #define CRCLENGTH 4 |
| |
| static inline void clear_pci_tx_desc_content(__le32 *__pdesc, u32 _size) |
| { |
| memset((void *)__pdesc, 0, |
| min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET)); |
| } |
| |
| struct tx_desc_92d { |
| u32 pktsize:16; |
| u32 offset:8; |
| u32 bmc:1; |
| u32 htc:1; |
| u32 lastseg:1; |
| u32 firstseg:1; |
| u32 linip:1; |
| u32 noacm:1; |
| u32 gf:1; |
| u32 own:1; |
| |
| u32 macid:5; |
| u32 agg_en:1; |
| u32 bk:1; |
| u32 rdg_en:1; |
| u32 queuesel:5; |
| u32 rd_nav_ext:1; |
| u32 lsig_txop_en:1; |
| u32 pifs:1; |
| u32 rateid:4; |
| u32 nav_usehdr:1; |
| u32 en_descid:1; |
| u32 sectype:2; |
| u32 pktoffset:8; |
| |
| u32 rts_rc:6; |
| u32 data_rc:6; |
| u32 rsvd0:2; |
| u32 bar_retryht:2; |
| u32 rsvd1:1; |
| u32 morefrag:1; |
| u32 raw:1; |
| u32 ccx:1; |
| u32 ampdudensity:3; |
| u32 rsvd2:1; |
| u32 ant_sela:1; |
| u32 ant_selb:1; |
| u32 txant_cck:2; |
| u32 txant_l:2; |
| u32 txant_ht:2; |
| |
| u32 nextheadpage:8; |
| u32 tailpage:8; |
| u32 seq:12; |
| u32 pktid:4; |
| |
| u32 rtsrate:5; |
| u32 apdcfe:1; |
| u32 qos:1; |
| u32 hwseq_enable:1; |
| u32 userrate:1; |
| u32 dis_rtsfb:1; |
| u32 dis_datafb:1; |
| u32 cts2self:1; |
| u32 rts_en:1; |
| u32 hwrts_en:1; |
| u32 portid:1; |
| u32 rsvd3:3; |
| u32 waitdcts:1; |
| u32 cts2ap_en:1; |
| u32 txsc:2; |
| u32 stbc:2; |
| u32 txshort:1; |
| u32 txbw:1; |
| u32 rtsshort:1; |
| u32 rtsbw:1; |
| u32 rtssc:2; |
| u32 rtsstbc:2; |
| |
| u32 txrate:6; |
| u32 shortgi:1; |
| u32 ccxt:1; |
| u32 txrate_fb_lmt:5; |
| u32 rtsrate_fb_lmt:4; |
| u32 retrylmt_en:1; |
| u32 txretrylmt:6; |
| u32 usb_txaggnum:8; |
| |
| u32 txagca:5; |
| u32 txagcb:5; |
| u32 usemaxlen:1; |
| u32 maxaggnum:5; |
| u32 mcsg1maxlen:4; |
| u32 mcsg2maxlen:4; |
| u32 mcsg3maxlen:4; |
| u32 mcs7sgimaxlen:4; |
| |
| u32 txbuffersize:16; |
| u32 mcsg4maxlen:4; |
| u32 mcsg5maxlen:4; |
| u32 mcsg6maxlen:4; |
| u32 mcsg15sgimaxlen:4; |
| |
| u32 txbuffaddr; |
| u32 txbufferaddr64; |
| u32 nextdescaddress; |
| u32 nextdescaddress64; |
| |
| u32 reserve_pass_pcie_mm_limit[4]; |
| } __packed; |
| |
| void rtl92de_tx_fill_desc(struct ieee80211_hw *hw, |
| struct ieee80211_hdr *hdr, u8 *pdesc, |
| u8 *pbd_desc_tx, struct ieee80211_tx_info *info, |
| struct ieee80211_sta *sta, |
| struct sk_buff *skb, u8 hw_queue, |
| struct rtl_tcb_desc *ptcb_desc); |
| bool rtl92de_is_tx_desc_closed(struct ieee80211_hw *hw, |
| u8 hw_queue, u16 index); |
| void rtl92de_tx_polling(struct ieee80211_hw *hw, u8 hw_queue); |
| void rtl92de_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, |
| struct sk_buff *skb); |
| |
| #endif |
